![](bg4.png)
post-synthesis outcome suggested a maximum clock
frequency of 400 MHz, with enough timing and
power margins. Again, re-analysis shows that for
a similar design scaled for block length 1057, this
implementation would have had a throughput of 6
Gbps. This is very close to the highest throughput
reported for an ASIC design reported so far, 7 Gbps
in (Mohsenin et al., 2009) using 65 nm technology.
The area of our implementation was estimated as
1.99 mm
2
, and average power dissipation as 23.2
mW, at V
cc
= 1.2 V.
7.3 Simulation Results
Detailed simulations show the good BER perfor-
mance of this implementation, assuming an AWGN
channel and BPSK modulation scheme. Our calcula-
tions show that the length-1057 code’s transmission
rate is within 0.03 bits/sec of Shannon capacity limit
over Binary Symmetric Channel.
7.4 Comparative Analysis
Our designs use PG structure of LDPC codes, that
have not been reported for decoder design before. In
general, PG codes converge very fast under SPA de-
coding(Kou et al., 2001), as well as for log-SPA de-
coding. This is because given the medium code rates
of PG codes, there are more parity checks updating
each bit probability, leading to faster convergence,
and hence higher throughput. Especially in 2
nd
de-
sign, a novel micro-architecture of bit and check pro-
cessing units for higher degree nodes was evolved,
which has also not been reported until now. This
micro-architecture was able to meet more aggressive
timing constraints, and hence higher throughput.
8 CONCLUSIONS
We have reported two novel LDPC decoder designs
that are based on projective geometry structure of
LDPC codes. The throughputs of both designs ex-
ceed the requirements of various standards, with sec-
ond design’s throughput being many times greater
than required. BER and convergence performances
of both the decoders have also been found satisfac-
tory. The 1
st
design is currently undergoing further
system-level optimizations such as circuit retiming,
and elimination of multipliers. Based on the learn-
ing that wires are a limiting resources on a FPGA for
this decoder, a completely new superscalar pipelined
architecture is also currently being designed.
FPGAs are heavily resource limited, and hence we
could not fit code of length more than 73, even though
the design is capable of handling any-length decod-
ing. A more pragmatic approach is to fold the geom-
etry, and map the folded geometry on the decoder’s
interconnect. A novel design for such semi-parallel
decoder architecture, based on symmetry and regular-
ity of projective geometry, was patented in (Sharma,
2007). In fact, we have found more applications of
PG-based interconnect in CD-ROM/DVD-R decod-
ing (Adiga et al., 2010) as well as matrix computa-
tions, and hence are convinced of its potential.
ACKNOWLEDGEMENTS
The authors are grateful to Tata Consultancy Services
for funding the research project under project code no.
1009298.
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