![](bg8.png)
proposed in this paper. In a traditional NoC design,
the router architectures have fixed allocated buffer
space for each input channel. With communication
in future heterogeneous SoC architectures, especially
with running different applications with different
traffic patterns at different times, this will prove
highly inefficient due to the router resources not
getting utilised effectively, causing wastage of buffer
capacities. The proposed router architecture
endeavours to solve this problem, by using a fully
flexible ring buffer structure which can be shared
between all channels of router. The buffer size of
each channel will be allocated from the ring buffer
which can vary from a single buffer unit, when there
is no traffic on that channel, up to the whole buffer
length of the ring buffer which represents all
dedicated buffer resources of the router. Therefore,
the proposed router allocates buffer sizes at runtime
according to the traffic rate of each channel. This
router architecture enables utilisation of all available
buffer resources effectively and improves the quality
of service in the NoCs. A simple mechanism has also
been proposed to avoid deadlock and to make sure
that there is at least an escape channel for the
blocked messages to proceed.
Although RTL implementation results showed an
increase of area, this architecture proved its
superiority in terms of power consumption as well as
memory overhead compared to the DB architecture.
Moreover, our extensive simulation study has shown
the effectiveness of this approach in improving the
network performance. In all simulations scenarios,
the proposed architecture has
experienced lower
message latency under heavy moderate to traffic and
even when the network starts to approach saturation.
Furthermore, it has been shown that the maximum
sustained load of the proposed router is up to 20%
higher than that of a traditional router.
REFERENCES
International Technology Roadmap for Semiconductors
web site http://public.itrs.net.
W. J. Dally and B. Towles, "Route Packets, Not Wires:
On-Chip Interconnection Networks," in Proceedings
of the Design Automation Conference (DAC), 2001.
P. Guerrier and A. Greiner, "A generic architecture for on-
chip packet-switched interconnections," in
Proceedings of the Design, Automation and Test in
Europe Conference and Exhibition (DATE), pp. 250-
256, 2000.
A. Hemani, A. Jantsch, S. Kumar, A. Postula, J. Öberg, M.
Millberg, and D. Lindqvist, “Network on a Chip: An
architecture for billion transistor era”, Proceeding of
the IEEE NorChip Conference, 2000.
L. Benini and G. D. Micheli. Networks on Chip: A New
SoC Paradigm. IEEE Computer, 35(1):70–78, 2002.
C. Bobda, A. Ahmadinia, M. Majer, J. Teich, S. Fekete,
and J. Van der Veen. DyNoC: A Dynamic
Infrastructure for Communication in Dynamically
Reconfigurable Devices. In Field-Programmable
Logic and Applications, International Conference,
pages 153–158, 2005.
C. Xuning and L. S. Peh, "Leakage power modeling and
optimization in interconnection networks," in
Proceedings of the International Symposium on Low
Power Electronics and Design (ISLPED), pp. 90-95,
2003.
H. Jingcao and R. Marculescu, "Application-specific
buffer space allocation for networks-on-chip router
design," in Proceedings of the IEEE/ACM
International Conference on Computer Aided Design
(ICCAD), pp. 354-361, 2004.
C. Bobda and A. Ahmadinia, Dynamic interconnection of
reconfigurable modules on reconfigurable devices,
Design and Test of Computers IEEE 22 (5) (2005),
pp. 443–451.
J. H. Bahn, S. E. Lee, and N. Bagherzadeh, "Design of a
router for network-on-chip," International Journal of
High Performance Systems Architecture 2007 - Vol.
1, No.2 pp. 98 - 105.
M. Kreutz, A. Cesar, M. Luigi, C. Flavio, W. Altamiro
and A. Susin, “Design space exploration comparing
homogeneous and heterogeneous network-on-chip
architectures”, Proc. of Symposium on Integrated
Circuits and System Design, 2005, pp. 190–195.
S. Lee, N. Bagherzadeh, "Increasing the Throughput of an
Adaptive Router in Network-on-Chip (NoC), " in the
Proc. of Int'l Conference on Hardware/Software
Codesign and System Synthesis (CODES+ISSS), Oct.
2006.
B. Ahmad, A. Ahmadinia, and T. Arslan. Dynamically
Reconfigurable NoC with Bus Based Interface for
Ease of Integration and Reduced Design Time. In
Proc. of NASA/ESA Conference on Adaptive
Hardware and Systems. pp. 309-314, June 22-25,
2008.
M. A. Al Faruque, T. Ebi, J. Henkel: "ROAdNoC:
Runtime Observability for an Adaptive Network on
Chip Architecture", in Int'l Conference on Computer-
Aided Design. ICCAD 2008. 543-548.
D. Matos, C. Concatto, A. Kologeski, L. Carro, F.
Kastensmidt, A. Susin, and M. Kreutz. Adaptive
router architecture based on traffic behavior
observability. In Proc.s of intl. Workshop on Network
on Chip Architectures, New York, December 2009.
Xilinx XPower, http://www/xilinx.com
PECCS 2011 - International Conference on Pervasive and Embedded Computing and Communication Systems
412