IMAGE PROCESSING FRAMEWORK FOR FPGAS - Introducing a Plug-and-play Computer Vision Framework for Fast Integration of Algorithms in Reconfigurable Hardware
Bennet Fischer, Raul Rojas
2012
Abstract
This paper presents a framework for computer vision tasks on Field Programmable Gate Arrays (FPGA) which allows rapid integration of vision algorithms by separating the framework from the vision algorithms. A vision system can be created by using plug-and-play methodology. On an abstract level several input and output channels of the system can be defined. Also, commonly used image transformations are modularized and can be added to the inputs or outputs of an algorithm. Special input and output modules allow the integration of algorithms with no knowledge of the surrounding framework.
References
- BDTI (2010). The AutoESL AutoPilot High-Level Synthesis Tool. http://www.bdti.com/MyBDTI/pubs/AutoPilot.pdf.
- Bouguet, J. (1999). Pyramidal implementation of the lucas kanade feature tracker description of the algorithm. Intel Corporation, Microprocessor Research Labs, OpenCV Documents, 3(2):1-9.
- Cope, B., Cheung, P., Luk, W., and Howes, L. (2009). Performance comparison of graphics processors to reconfigurable logic: A case study. IEEE Transactions on Computers, 59(4):433-448.
- Jin, Q., Thomas, D., and Luk, W. (2009). Exploring reconfigurable architectures for explicit finite difference option pricing models. In Field Programmable Logic and Applications, 2009. FPL 2009. International Conference on, volume 54, pages 73-78. IEEE.
- Kalomiros, J. and Lygouras, J. (2008). Design and evaluation of a hardware/software FPGA-based system for fast image processing. Microprocessors and Microsystems, 32(2):95-106.
- Lucas, B. and Kanade, T. (1981). An iterative image registration technique with an application to stereo vision. In Proceedings of the 7th International Joint Conference on Artificial Intelligence (IJCAI), pages 674-679.
- van der Wal, G., Brehm, F., Piacentino, M., Marakowitz, J., Gudis, E., Sufi, A., and Montante, J. (2006). An FPGA-based verification framework for real-time vision systems. Pattern Recognition, 2.
Paper Citation
in Harvard Style
Fischer B. and Rojas R. (2012). IMAGE PROCESSING FRAMEWORK FOR FPGAS - Introducing a Plug-and-play Computer Vision Framework for Fast Integration of Algorithms in Reconfigurable Hardware . In Proceedings of the 2nd International Conference on Pervasive Embedded Computing and Communication Systems - Volume 1: PECCS, ISBN 978-989-8565-00-6, pages 295-300. DOI: 10.5220/0003801402950300
in Bibtex Style
@conference{peccs12,
author={Bennet Fischer and Raul Rojas},
title={IMAGE PROCESSING FRAMEWORK FOR FPGAS - Introducing a Plug-and-play Computer Vision Framework for Fast Integration of Algorithms in Reconfigurable Hardware},
booktitle={Proceedings of the 2nd International Conference on Pervasive Embedded Computing and Communication Systems - Volume 1: PECCS,},
year={2012},
pages={295-300},
publisher={SciTePress},
organization={INSTICC},
doi={10.5220/0003801402950300},
isbn={978-989-8565-00-6},
}
in EndNote Style
TY - CONF
JO - Proceedings of the 2nd International Conference on Pervasive Embedded Computing and Communication Systems - Volume 1: PECCS,
TI - IMAGE PROCESSING FRAMEWORK FOR FPGAS - Introducing a Plug-and-play Computer Vision Framework for Fast Integration of Algorithms in Reconfigurable Hardware
SN - 978-989-8565-00-6
AU - Fischer B.
AU - Rojas R.
PY - 2012
SP - 295
EP - 300
DO - 10.5220/0003801402950300