Table 2: Impact of improvements; individually and combined. All values are for a 7x1 implementation.
Approach Non-Occ % All % Disc % Slices LUTs
SAD 29.1 30.7 27.4 1,221 6,086
LRC 40.5 41.9 40.1 2,399 7,689
Median 22.2 23.9 24.3 1,468 6,371
LRC-Med 38.6 39.9 39.5 3,135 8,204
LRC-Prop 27.2 28.4 24.9 3,174 8,237
LRC-Med-Prop 31.1 32.0 28.8 3,986 8,844
LRC-Prop-Med 20.4 21.8 21.7 3,986 8,844
Available 33,280 33,280
through confidence assessment, could render a sub-
stantial improvement together with a competent prop-
agation method. Implementing a small confidence
measurement would be a good continuance of this
work.
It is further evident that it is possible to achieve
acceptable disparity maps without extensive mem-
ory usage and without a limitation on image size.
Megapixel images will not affect the throughput or
the resource utilization of the suggested approach as
image data is only stored in a shift register approach
without the need for multi-scanline retention. Fur-
thermore, the 1D implementation is resource reduced,
and can be fitted to practically any FPGA. It has been
implemented with a maximum disparity range of 64
for images of 1024x1024 pixels.
The implementations run at 125 MHz, the system
clock of the FPGA-board (Lidholm et al., 2008). As
the implementations are fully piped, the frame rate is
dependent on the speed of the cameras and the size of
the frame. Theoretically, it is capable of processing
over 100 frames per second for Megapixel images.
ACKNOWLEDGEMENTS
The authors would like to acknowledge Xilinx for
their kind donation of our FPGA’s and design soft-
ware tools, Hectronic for the design and manufactur-
ing of our FPGA boards, and The Knowledge Foun-
dation for providing funding for the project.
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