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4 CONCLUSIONS
FPGAs have become one of the most important
platforms to implement dedicate 2D/3D graphic
accelerators. Due to their flexibility and their good
low-volume price, FPGA based solutions are
preferred in applications fields where the display
technology is changing frequently or the end market
does not support high volume sales. A wide range of
graphic IPs have been developed for reconfigurable
devices, both industrial and academic. These
approaches implement a more general rendering
pipeline, on which graphic operations are
“programmed”. Many of the graphic IPs can be used
for implementing the entire OpenGL set of
operations.
Automatic generation tools for hardware IPs for
FPGA have been developed for floating point units,
discrete Fourier transform or FIR filters. The goal of
these approaches is to optimize a specific set of
operations which can be used for a very narrow
range of applications. One project which exemplifies
this type of approach is represented by the FloPoCo
project, which aims at delivering hardware for any
given set of arithmetic operations. The optimizations
of such system result from the elimination of
redundant micro-operations, such as normalizations
or roundings.
This type of approach can also be used for
dedicated graphic pipelines. The generated hardware
will implement only the required sub-operations of
the graphic pipeline, with a lower hardware cost and
a possible performance improvement. This way, a
restricted set of OpenGL functions, which are
specific to a narrow range of applications, can be
used on the generated graphic engine. The approach
relies on the high flexibility offered by FPGAs, a
different type of graphic application requiring a
different accelerator IP.
ACKNOWLEDGEMENTS
This work was partially supported Romanian
National Authority for Research CNCS –
UEFISCDI project PN-II-RU-TE-2011-3-0186.
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