in waiting requests rate from 0.049 to 0.056.(1.14
times more).
During every simulation process, we note both the
CPU and the memory load percentage. As shown in
figure 4, the CPU load percentage for the inter-arrival
time 1/λ=30ms is 70% and it increases only to 82%
for the inter-arrival time 1/λ=10ms. In addition, the
memory load is nearly constant for the different sim-
ulations processes which show the good performance
of our TDRBAC system.
7 CONCLUSIONS AND FUTURE
WORK
In this work, we have presented an overview of our
access control model called TDRBAC. This model
is designed using the agent technology which satis-
fies context-awareness and scalability system require-
ments, and it is implemented using JADE platform.
The performance tests of the prototype implementa-
tion show that the system is scalable for thousands
of requests. In the future, we intend to stress the
system with more requests and to duplicate the over-
loaded TDRBAC system agents. In addition, we plan
to test our system with different system configura-
tions such as roles number, views number, context at-
tributes number, etc. Finally, we aim to test our sys-
tem efficiency by applying different attack scenarios.
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