Verification and Validation of Meta-model based Transformation from SysML to VHDL-AMS

Jean-Marie Gauthier, Fabrice Bouquet, Ahmed Hammad, Fabien Peureux

2013

Abstract

This paper proposes an approach to verify SysML models consistency and to validate the transformation of SysML models to VHDL-AMS code. This approach is based on two main solutions: the use of model-to-model transformation to verify SysML models consistency and writing unit tests to validate model transformations. The translation of SysML models into VHDL-AMS simulable code uses MMT (Model to Model Transformation) ATL Atlas Transformation Language and M2T (Model To Text) Acceleo tooling. The test validation of the model transformations is performed using EUNIT framework.

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Paper Citation


in Harvard Style

Gauthier J., Bouquet F., Hammad A. and Peureux F. (2013). Verification and Validation of Meta-model based Transformation from SysML to VHDL-AMS . In Proceedings of the 1st International Conference on Model-Driven Engineering and Software Development - Volume 1: MODELSWARD, ISBN 978-989-8565-42-6, pages 123-128. DOI: 10.5220/0004317601230128


in Bibtex Style

@conference{modelsward13,
author={Jean-Marie Gauthier and Fabrice Bouquet and Ahmed Hammad and Fabien Peureux},
title={Verification and Validation of Meta-model based Transformation from SysML to VHDL-AMS},
booktitle={Proceedings of the 1st International Conference on Model-Driven Engineering and Software Development - Volume 1: MODELSWARD,},
year={2013},
pages={123-128},
publisher={SciTePress},
organization={INSTICC},
doi={10.5220/0004317601230128},
isbn={978-989-8565-42-6},
}


in EndNote Style

TY - CONF
JO - Proceedings of the 1st International Conference on Model-Driven Engineering and Software Development - Volume 1: MODELSWARD,
TI - Verification and Validation of Meta-model based Transformation from SysML to VHDL-AMS
SN - 978-989-8565-42-6
AU - Gauthier J.
AU - Bouquet F.
AU - Hammad A.
AU - Peureux F.
PY - 2013
SP - 123
EP - 128
DO - 10.5220/0004317601230128