![](bg2.png)
Figure 1: System configuration.
technologies, particularly FTL and buffer cache, for
these non-volatile memories. In Section 3, we
present a novel buffer cache scheme called HAC.
Section 4 presents the experimental results. Finally,
Section 5 concludes the paper.
2 BACKGROUND
2.1 Software for NAND Flash Memory
A NAND flash memory is organized in terms of
blocks, where each block is of a fixed number of
pages. A block is the smallest unit of erase
operation, while reads and writes are handled by
pages. Flash memory cannot be written over existing
data unless erased in advance. The number of times
an erasure unit can be erased is limited. The erase
operation can only be performed on a full block and
is slow that usually decreases system performance.
In order to solve erase-before-write problem, a kind
of device driver called FTL is usually implemented
in OS. The FTL performs the physical-to-logical
address translation to reduce the number of erase
operations. Most address translation schemes use a
log block mechanism for storing updates.
A log block scheme, called block associative
sector translation (BAST), was proposed by (Kim et
al., 2002). In the BAST scheme, flash memory
blocks are divided into data blocks and log blocks.
Data blocks represent the ordinary storage space and
log blocks are used for storing updates. When an
update request arrives, the FTL writes the new data
temporarily in the log block, thereby invalidating the
corresponding data in the data block. In BAST,
whenever the free log blocks are exhausted, in order
to reclaim the log block and the corresponding data
block, the valid data from the log block and the
corresponding data block should be copied into an
empty data block. This is called a merge operation.
After the merge operation, two erase operations need
to be performed in order to empty the log block and
the old data block. When the data block is updated
sequentially starting from the first page to the last
page, the FTL can apply a simple switch merge,
which requires only one erase operation and no copy
operations.
Further, there have been studies on buffer caches
schemes considering flash memory storages. A
page-level scheme called clean first least recently
used (CFLRU) was proposed by (Park et al., 2006).
CFLRU maintains a page list by LRU order and
divides the page list into two regions, namely the
working region and clean-first region. In order to
reduce the write cost, CFLRU first evicts clean
pages in the clean-first region by the LRU order, and
if there are no clean pages in the clean-first region, it
evicts dirty pages by their LRU order. CFLRU can
reduce the number of write and erase operations by
delaying the flush of dirty pages in the page cache.
Also, a block-level buffer cache scheme called
block padding LRU (BPLRU) was proposed, which
considers the block merge cost in the log block FTL
schemes (Kim and Ahn, 2008). BPLRU maintains a
LRU list based on the flash memory block.
Whenever a page in the buffer cache is referenced,
all pages in the same block are moved to the MRU
position. When buffer cache is full, BPLRU scheme
evicts all the pages of a victim block but it simply
selects the victim block at the LRU position. In
addition, it writes a whole block into a log block by
the in-place scheme using the page padding
technique. In page padding procedure, BPLRU reads
some pages that are not in the victim block, and
writes all pages in the block sequentially. The page
padding may perform unnecessary reads and writes,
but it is effective because it can change an expensive
full merge to an efficient switch merge. In BPLRU,
all log blocks can be merged by the switch merge,
which results in decreasing the number erase
operations.
2.2 Software for PRAM
A PRAM cell uses a special material, called phase
change material, to represent a bit. PRAM density is
expected to be much greater than that of DRAM
(about four times). Further, PRAM has negligible
leakage energy regardless of the size of the memory.
Though PRAM has attractive features, the write
access latency of PRAM is not comparable to that of
DRAM. Also, PRAM has a worn-out problem
caused by limited write endurance. Since the write
operations on PRAM significantly affect the
ABufferCacheSchemeConsideringBothDRAM/PRAMHybridMainMemoryandFlashMemoryStorages
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