![](bg9.png)
heads in the study of such scheduling policies is to
use a cycle-accurate simulator or a real system.
There are two major simulator available. The first
one, Gem5 is the merger of the M5 and GEMS simu-
lators (Binkert et al., 2011). It simulates a full system
with various CPU models and a flexible memory sys-
tem that includes caches. The second one, Simics, is a
commercial product able to simulate full-systems but
it is not cycle-accurate (Magnusson et al., 2002).
LITMUS
RT
(Calandrino et al., 2006), developed
at the University of North Carolina (UNC), offers a
different approach. It is not a simulator but an exten-
sion of the Linux Kernel which provides an exper-
imental platform for applied real-time research and
that supports a large number of real-time multipro-
cessor schedulers.
With both kind of tools, a substantial investment
in time is required to learn how to use them and to
write some new scheduler components.
There are also several tools emerging from the
academic community and dedicated to the simula-
tion of real-time systems such as Cheddar (Singhoff
et al., 2004), MAST (Harbour et al., 2001),
Storm (Urunuela et al., 2010) and others (Rodr´ıguez-
Cayetano, 2011; Chandarli et al., 2012). Most of
these tools are designed to validate, test and analyze
systems. Storm is probably the most advanced tool
focusing on the study of the scheduler itself. However
it does not handle direct overheads such as context-
switches or scheduling overheads. Nor does it handle
the impact of caches.
9 CONCLUSIONS
This paper presents a simulator dedicated to the study
of real-time scheduling. It was designed to be easy
to use, fast and flexible. Our main contribution,
when compared to the existing scheduling simulators,
is the integration of overheads linked to the system
(context-switching, scheduling decision) and the im-
pact of the caches.
We have shown in this paper that it is possible
to take the impact of the caches into consideration.
However, the models we currently use could proba-
bly be replaced by better ones. This replacement can
easily be done as explained in section 6. We are al-
ready thinking about new models but they have to be
validated using cycle accurate simulators.
Once our cache models will be validated and inte-
grated into the simulator, we will launch a large cam-
paign of simulations. As a reminder, our long term
goal is the classification of the numerous scheduling
policies with practical considerations. We hope that it
will also help the researchers to spot the weaknesses
and the strengths of the various strategies. We would
be pleased if our simulation tool could be the source
of innovative ideas.
ACKNOWLEDGEMENTS
The work presented in this paper was conducted
under the research project RESPECTED (http://anr-
respected.laas.fr/) which is supported by the French
National Agency for Research (ANR), program
ARPEGE.
REFERENCES
Anderson, J., Calandrino, J., and Devi, U. (2006). Real-
time scheduling on multicore platforms. In Proc. of
the 12th IEEE Real-Time and Embedded Technology
and Applications Symposium (RTAS).
Babka, V., Libiˇc, P., Martinec, T., and T˚uma, P. (2012). On
the accuracy of cache sharing models. In Proc. of the
third joint WOSP/SIPEW International Conference on
Performance Engineering (ICPE).
Bastoni, A., Brandenburg, B., and Anderson, J. (2010). An
empirical comparison of global, partitioned, and clus-
tered multiprocessor edf schedulers. In Proc. of the
IEEE 31st Real-Time Systems Symposium (RTSS).
Bastoni, A., Brandenburg, B., and Anderson, J. (2011). Is
semi-partitioned scheduling practical? In Proc. of
the 23rd Euromicro Conference on Real-Time Systems
(ECRTS).
Berna, B. and Puaut, I. (2012). Pdpa: period driven task and
cache partitioning algorithm for multi-core systems.
In Proc. of the 20th International Conference on Real-
Time and Network Systems (RTNS).
Binkert, N., Beckmann, B., Black, G., Reinhardt, S. K.,
Saidi, A., Basu, A., Hestness, J., Hower, D. R., Kr-
ishna, T., Sardashti, S., Sen, R., Sewell, K., Shoaib,
M., Vaish, N., Hill, M. D., and Wood, D. A. (2011).
The gem5 simulator. SIGARCH Computer Architec-
ture News.
Calandrino, J. M., Leontyev, H., Block, A., Devi, U. C., and
Anderson, J. H. (2006). Litmus
RT
: A testbed for em-
pirically comparing real-time multiprocessor sched-
ulers. In Proc. of the 27th IEEE International Real-
Time Systems Symposium (RTSS).
Chandarli, Y., Fauberteau, F., Masson, D., Midonnet, S.,
and Qamhieh, M. (2012). Yartiss: A tool to visual-
ize, test, compare and evaluate real-time scheduling
algorithms. In 3rd International Workshop on Analy-
sis Tools and Methodologies for Embedded and Real-
time Systems (WATERS).
Chandra, D., Guo, F., Kim, S., and Solihin, Y. (2005). Pre-
dicting inter-thread cache contention on a chip multi-
processor architecture. In Proc. of the 11th Inter-
national Symposium on High-Performance Computer
Architecture (HPCA).
SimulationofReal-timeMultiprocessorSchedulingwithOverheads
13