Use of Partial Reconfiguration for the Implementation and Embedding of the Artificial Neural Network (ANN) in FPGA

Carlos Alberto de Albuquerque Silva, Anthony Andrey Ramalho Diniz, Adrião Duarte Dória Neto, Jose Alberto Nicolau de Oliveira

2014

Abstract

This paper is focused on partial reconfiguration of Field Programmable Gate Arrays (FPGAs) Virtex$\circledR$-6, produced by Xilinx$\circledR$, and its application implementing Artificial Neural Networks (ANNs) of Multilayer Perceptron (MLP) type. This FPGA can be partially reprogramed without suspending operation in other parts that do not need reconfiguration. It can be performed by specifying the Modular Project’s flow, where the modules that compose the project can be synthesized separately, and, after that, reunited in another module of highest hierarchical level. Alternatively, it is possible developing reconfigurable modules inserted in partial bitstreams and, later, downloading partial bitstreams successively in hardware. Therefore, it is possible configuring topologies of different MLP networks by using partial bitstreams in reconfigurable areas. It is expected that, in this kind of hardware, applications with MLP ANNs be easily embedded, and also allow easily configuration of many kinds of MLP networks in field.

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Paper Citation


in Harvard Style

Alberto de Albuquerque Silva C., Andrey Ramalho Diniz A., Duarte Dória Neto A. and Alberto Nicolau de Oliveira J. (2014). Use of Partial Reconfiguration for the Implementation and Embedding of the Artificial Neural Network (ANN) in FPGA . In Proceedings of the 4th International Conference on Pervasive and Embedded Computing and Communication Systems - Volume 1: PECCS, ISBN 978-989-758-000-0, pages 142-150. DOI: 10.5220/0004716301420150


in Bibtex Style

@conference{peccs14,
author={Carlos Alberto de Albuquerque Silva and Anthony Andrey Ramalho Diniz and Adrião Duarte Dória Neto and Jose Alberto Nicolau de Oliveira},
title={Use of Partial Reconfiguration for the Implementation and Embedding of the Artificial Neural Network (ANN) in FPGA},
booktitle={Proceedings of the 4th International Conference on Pervasive and Embedded Computing and Communication Systems - Volume 1: PECCS,},
year={2014},
pages={142-150},
publisher={SciTePress},
organization={INSTICC},
doi={10.5220/0004716301420150},
isbn={978-989-758-000-0},
}


in EndNote Style

TY - CONF
JO - Proceedings of the 4th International Conference on Pervasive and Embedded Computing and Communication Systems - Volume 1: PECCS,
TI - Use of Partial Reconfiguration for the Implementation and Embedding of the Artificial Neural Network (ANN) in FPGA
SN - 978-989-758-000-0
AU - Alberto de Albuquerque Silva C.
AU - Andrey Ramalho Diniz A.
AU - Duarte Dória Neto A.
AU - Alberto Nicolau de Oliveira J.
PY - 2014
SP - 142
EP - 150
DO - 10.5220/0004716301420150