A 6GS/S 8-Bit Current Steering DAC with Optimized Current Switch Drive

Wenyuan Li, Juan Zhang, Chuyang Sun

2017

Abstract

A 6GS/s 8-bit current-steering DAC in 0.13μm CMOS technology is presented. The 5-31 binary to thermometer decoder and the switch drive signal are optimized, leading to obvious improvements in dynamic performance. A minimum spurious free dynamic range (SFDR) of 34 dB has been achieved over the full Nyquist bandwidth at 6GS/s. Total system power consumption is 95.44mW at 6GS/s with 2.98GHz input signal. Core area of DAC occupies 0.13mm2 without pads.

Paper Citation

in Harvard Style

Li W., Zhang J. and Sun C. (2017). A 6GS/S 8-Bit Current Steering DAC with Optimized Current Switch Drive . In Proceedings of the 7th International Joint Conference on Pervasive and Embedded Computing and Communication Systems - Volume 1: SPCS, (PECCS 2017) ISBN 978-989-758-266-0, pages 71-75. DOI: 10.5220/0006413100710075

in Bibtex Style

@conference{spcs17,
author={Wenyuan Li and Juan Zhang and Chuyang Sun},
title={A 6GS/S 8-Bit Current Steering DAC with Optimized Current Switch Drive},
booktitle={Proceedings of the 7th International Joint Conference on Pervasive and Embedded Computing and Communication Systems - Volume 1: SPCS, (PECCS 2017)},
year={2017},
pages={71-75},
publisher={SciTePress},
organization={INSTICC},
doi={10.5220/0006413100710075},
isbn={978-989-758-266-0},
}

in EndNote Style

TY - CONF
JO - Proceedings of the 7th International Joint Conference on Pervasive and Embedded Computing and Communication Systems - Volume 1: SPCS, (PECCS 2017)
TI - A 6GS/S 8-Bit Current Steering DAC with Optimized Current Switch Drive
SN - 978-989-758-266-0
AU - Li W.
AU - Zhang J.
AU - Sun C.
PY - 2017
SP - 71
EP - 75
DO - 10.5220/0006413100710075