An Energy Aware Scheduling for Reconﬁgurable Heterogeneous Systems

Ines Ghribi

, Riadh Ben Abdallah

and Mohamed Khalgui

1,2

LISI Laboratory, National Institute of Applied Sciences and Technology, University of Carthage, Tunis, Tunisia

Faculty of Science of Tunis, University of Tunis el Manar, Tunis, Tunisia

Keywords:

Embedded Systems, Scheduling, Probability, DVFS.

Abstract:

One of the major challenges of computer system design is the management and conservation of energy while

satisfying QoS requirements. Recently, Dynamic Voltage and Frequency Scaling (DVFS) has been integrated

to various embedded processors as a mean to increase the battery life without affecting the responsiveness

of tasks. This paper proposes an enhancement for I-codesign methodology [1] optimizing the energy con-

sumption of the designed system.We propose an energy aware real-time scheduling algorithm. This algorithm

makes use of the defferable server for the scheduling of aperiodic tasks along with DVFS. Simulation results

demonstrate a decrease in the resulting energy consumption compared to the previously published work.

1 INTRODUCTION

Energy consumption is one of the major limiting fac-

tors of battery powered real-time systems. In this con-

text, optimizing energy consumption without affect-

ing performance while satisfying real time constraints

is of major interest. To meet the timing constraints

of the system, a scheduler must coordinate a set of

tasks at different states (idle, blocked, running) and

asks the run-time system to allocate the required re-

sources to their execution. Many objectives must be

considered in the design of a scheduling algorithm: (i)

Guarantee that tasks with hard timing constraints will

always meet their deadlines, (ii) Attain a high degree

of schedulable utilization for hard deadline tasks, (iii)

Provide fast average response time for tasks with soft

deadlines (aperiodic tasks).

To obtain an energy-efﬁcient design, the Dynamic

Voltage and Frequency Scaling (DVFS) feature is

widely adopted in modern processors (Horowitzet al.,

1994). The basic idea of the DVFS strategy is to re-

duce a processor’s processing frequency, as long as

task’s timing constraints are not violated. Indeed, the

power consumption of the processor is a polynomial

of the processing frequency, generally with a degree

no less than 2 (Li, 2012), while the overall execution

time of a task is just inversely proportional to the pro-

cessing frequency. DVFS provides the possibility of

minimizing energy consumption given a certain per-

formance/timing requirement.

In an early work, we proposed a methodology

called I-codesign for reconﬁgurableco-design (Ghribi

et al., 2016a). I-codesign presents an abstract model

for hardware/software systems allowing early explo-

ration of hardware/software trade-offs and evaluation

of design alternatives. This model supports incremen-

tal reﬁnement and evaluation at multiple abstraction

levels. Its aim is to lead to an efﬁcient implementation

and improve overall system performance. The entry

point for I-codesign is a hardware/software speciﬁ-

cation modeled by a DAG (Directed Acyclic Graph)

where nodes are software functions. I-codesign maps

this speciﬁcation into a hardware architecture that is

mainly an MPSoC. It also deﬁnes a new partition-

ing and mapping techniques for the proposed hard-

ware/software model: a functional algorithm fol-

lowed by a constructive algorithm and ﬁnally an it-

erative algorithm for optimization. Based on several

design constraints such as inclusion/exclusion, com-

munication costs, energy, memory, real-time feasibil-

ity and probabilistic estimations, I-codesign takes de-

cisions of near-optimal placement of software func-

tions into the target hardware units.

In this paper, we investigate the opportunity of re-

ducing power consumption of the system to be de-

signed according to I-codesign methodology and thus

by introducing the DVFS feature in the proposed

scheduling algorithm. We study the scheduling of

a heteregenous task set modeled and partitioned ac-

cording to the I-codesign methodology. An energy

aware real-time scheduling algorithm for probabilis-

tic heterogeneous task set is introduced in order to

enhance the I-codesign power consumption and re-

sponse time metrics. DVFS is applied on periodic

Ghribi, I., Abdallah, R. and Khalgui, M.

An Energy Aware Scheduling for Reconﬁgurable Heterogeneous Systems.

DOI: 10.5220/0006460701710177

In Proceedings of the 12th International Conference on Software Technologies (ICSOFT 2017), pages 171-177

ISBN: 978-989-758-262-2

171

tasks in order to reduce energy consumption without

compromising periodic function deadlines and ape-

riodic functions responsiveness. In order to apply

the proposed scheduling algorithm periodic functions

priorities have been redeﬁned according to two con-

straints : (i) the edge probability connecting the func-

tion to their predecessors in the task DAG, (ii) Func-

tion hierarchy which refers to the level of the corre-

sponding function on the task DAG representation.

The originality of this work resides in including the

probabilistic estimation of the task’s execution not

only in the mapping process but also in the scheduling

algorithm. The consideration of the precedence con-

straint through the proposed DAG hierarchy rule does

cooperate and improve the overall system scheduling

performance.

The paper proceeds as follows. The next Sec-

tion describes useful background. Section III presents

the I-codesign methodology. In Section IV, the sys-

tem formalization and the notations used in this pa-

per are developed. Section V exposes the proposed

algorithm. Section VI shows simulation results of

scheduling of real-time tasks and ﬁnally we conclude

this paper in Section IV.

2 RELATED WORK

This section reviews the main approaches for schedul-

ing a mixture of aperiodic tasks and periodic hard

real-time tasks. The easiest way to prevent aperi-

odic tasks from interfering with periodic hard real-

time tasks is to schedule them as background tasks

executing only at times when there is no periodic task

ready for execution. Although this method guarantees

the schedulability of a periodic task, the execution

of aperiodic tasks may be delayed and their response

times are prolonged unnecessarily. The polling server

is a periodic task with a period Ts, a capacity Cs

and the highest priority (Li-yong et al., 2010). Ev-

ery server’s activation, it checks if there are any pend-

ing aperiodic tasks, if there are, the server uses its

capacity to service them until either the task is ﬁn-

ished or the server’s capacity is depleted. However,

if there is no pending aperiodic task, the server re-

mains idle until its next activation which means that

even if an aperiodic request occurs in the middle of

the server’s servicing time, the request will not be

treated until the next period as the server will already

be inactive (Liyong et al., 2010). The Priority Ex-

change (PE) and Deferrable Server (DS) algorithms,

introduced by Strosnider in (Strosnider et al., 1995),

overcome the drawbacks associated with polling and

background servicing of aperiodic requests. As with

polling, the PE and DS algorithms create a periodic

task (usually of a high priority) for servicing aperi-

odic requests. However, unlike polling, these algo-

rithms will preserve the execution time allocated for

aperiodic service if, upon the invocation of the server

task, no aperiodic requests are pending. These algo-

rithms can yield improved average response times for

aperiodic requests because of their ability to provide

immediate service for aperiodic tasks. The DS algo-

rithm maintains its aperiodic execution time for the

duration of the server’s period. Thus, aperiodic re-

quests can be serviced at the server’s high priority at

anytime as long as the server’s execution time for the

current period has not been exhausted. At the begin-

ning of the DS’s period, the server’s high priority ex-

ecution time is replenished to its full capacity. Unlike

the DS algorithm, the PE algorithm preserves its high

priority execution time by exchanging it for the exe-

cution time of a lower priority periodic task (Desokey

et al., 2006). The DS algorithm can provide better

aperiodic responsiveness than polling because it pre-

serves its execution time until it is needed by an ape-

riodic task. The DS algorithm is a simple algorithm

to implement than the PE algorithm, because the DS

algorithm always maintains its high priority execution

time at its original priority level and never exchanges

its execution time with lower priority levels as does

the PE algorithm. It also requires less memory space

than the PE and much lower computational complex-

ity.

During the past two decades, tremendous works

have been done regarding energy-aware scheduling

on DVFS-enabled platforms. The application of

DVFS algorithm to periodic task set is a well known

research area (Tchamgoue et al., 2012; Ansari et al.,

2013). However, few works in literature focuses on

DVFS applied to heterogeneous task set comprising

of periodic and aperiodic tasks (Dongkun and Jihong,

2004; Shin and Kim, 2006). The DVFS algorithm fo-

cuses on the usage and distribution of available slack

time. The total time required by a task to run com-

pletely i.e. the actual execution time (aet) is always

less than its worst case execution time (wcet). The

difference that exists is the slack and it in turn, is uti-

lized for reducing the voltage and frequency dynami-

cally.

This paper proposes a new scheduling algorithm with

original evaluation metrics for priority calculation

along with the defferable server for the scheduling

algorithm. In this work, DVFS is incorporated into

the scheduling process in order to dynamically rede-

ﬁne the scheduled element’s periodicity and reduce

the energy consumption.

ICSOFT 2017 - 12th International Conference on Software Technologies

172

3 I-CODESIGN METHODOLOGY

The goal of I-codesign is to achievea concurrent hard-

ware/software system design. It acts on a probabilis-

tic task model to a hardware architecture in a manner

that fulﬁlls all the system requirements and respects

the design constraints. I-codesign deals with a set of

models and transformations. The main idea behind I-

codesign is the use of the probabilistic task model in

mapping which embeds useful data for the mapping

and further optimization steps. Figure 1 presents the

ﬂow diagram of the I-codesign methodology.

I-Codesign Module

Functional Partioning

Hierarchical Partioning

Unsatisfied Constraint

Kernighan-Lin

Unsatisfied Constraint

Add Task to Mapping Table

Switch Cluster

Create Cluster

Switch Cluster

Create Cluster

Switch Cluster

Create Cluster

Figure 1: I-codesign methodology Flow Diagram.

The ﬁrst step is the functional partitioning algo-

rithm. It evaluates the inclusion/exclusion constraints

between task functions and creates clusters depending

on this constraint. Couples that are concerned with

inclusion or exclusion constraints are placed in either

the same or different clusters. Once all the inclusions

and exclusions are evaluated, a feasibility analysis is

performed. If all clustered functions sets on the cre-

ated clusters are schedulable on one of the available

processors then the schedulability test is validated.

Otherwise, the functional partitioning is applied again

to create new clusters with schedulable function sets.

Since any inclusion/exclusion constraint is hard, the

clustered tasks are locked and cannot be moved any

more. The second phase is the hierarchical partition-

ing algorithm. It clusters the remaining functions that

have no inclusion/exclusion constraints. The func-

tions are evaluated by their connecting edge’s prob-

abilities and high probability values are treated ﬁrst.

The available memory space is evaluated at each itera-

tion. Once all the remaining functions are placed into

clusters a feasibility analysis is performed. If all the

functions sets on the created clusters are schedulable

on one of the available processors then the schedu-

lability test is validated. Otherwise, the hierarchi-

cal clustering is applied again to generate clusters

with schedulable function sets. The last phase is the

kernighan-Linoptimization algorithm. This step eval-

uates both probability and communication cost on the

edges connecting functions by gain calculation. If the

gain is positive, then the function is moved to another

cluster if its energy consumption on the other cluster

is less or equal to its energy consumption on the orig-

inal cluster. Otherwise it is left on the original cluster.

4 SYSTEM MODEL AND

PROBLEM DEFINITION

4.1 Task Model

The software model comprises a set of tasks T

, i

∈ [1..N] represented by a directed acyclic graph T

, E

), where (i) V

is a set of nodes that corre-

spond to functions, and (ii) E

is a set of arcs which

describe connection between functions. The edges

are weighted with a couple ≺ Pr,Cc ≻ where Pr is

the probability of executing this edge and Cc is the

communication cost of data transfer between the two

nodes connected with the edge. A task T

is a set of n

periodic functions F= {F

, F

, .., F

}. Each function

is described by quadruplet F

= (R

, C

, P

, D

) where

is the phase, C

is the wcet, P

is the period and D

is the deadline of the i

periodic function. There are

m aperiodic functions A= {A

, A

, .., A

}. Each func-

tion A

is described by doublet A

= (Ar

, C

) where Ar

is the arrivaltime andC

is the execution time of the i

aperiodic function A

. Figure 2 presents an example

of the task model composed of six periodic functions

and two aperiodic functions. The following notations

are used in the rest of the paper:

• EdgeProba(F

) returns the highest probability of

the edges connecting F

to its predecessors; For

example EdgeProba(F

) returns 1,

• Level(F

) returns the level of F

on the DAG; For

example level(F

) returns 2.

We also deﬁned inclusion/exclusion constraint. It

is used to impose at a couple of functions and/or be-

haviors to be executed either on the same computing

unit or on different ones. The exclusion constraint

An Energy Aware Scheduling for Reconﬁgurable Heterogeneous Systems

173

0.5/10

0.4/8

0.7/9

0.1/6

0.3/12

0.2/5

1/7

1/13

Level2

Level1

Level3

Figure 2: A task graph.

is modeled within the task representation by marking

the symbol 6⊂ on the function F

which means that F

must not be executed with its predecessor on the same

computing unit. The inclusion constraint is modeled

by marking the symbol ⊂ on F

which means that F

must be executed with its predecessor on the same

computing unit.

4.2 Problem Deﬁnition

In a previouswork (Ghribi et al., 2016a), I-codesign is

described in detail. For a given task set, I-codesign is

applied and as a result we get an optimized mapping

of the system tasks into the hardware processing ele-

ments. The resulting mapping allows the execution of

all possible reconﬁgurable scenarios of the designed

system. It reduces the inter-PEs communications and

guarantees the schedulability of tasks.

I-codesign has been developed with the assumption

that all functions are periodic. In this work we address

the scheduling of heterogeneous task set scheduling

while reducing the overall energy consumption of the

system.

5 PROPOSED ALGORITHM AND

EXAMPLE

In this section we present a scheduling algorithm for

heterogeneous task set comprising periodic and aperi-

odic tasks. This algorithm relies on a deffrebaleserver

for aperiodic tasks. Aperiodic functions will be exe-

cuted at the maximum frequency and priority in or-

der to achieve lowest response time whereas utiliza-

tion of periodic functions will be updated according

to the DVFS algorithm. Thus, we deﬁned a defferable

server T

having a period denoted P

and a capacity

denoted C

. For periodic functions, a priority deﬁni-

tion is proposed as follows:

1. ∀ F

, F

∈ T

, if Level(F

)

∨

Level(F

), then

priority(F

)

∨

priority(F

2. ∀ F

, F

∈ T

, if Level(F

)=Level(F

) and

EdgeProba(F

)

∨

EdgeProba(F

), then

priority(F

)

∨

priority(F

5.1 Scheduling Algorithm

The inputs of the proposed algorithm are the follow-

ing : (i) H is the hyper-period of all the periodic tasks

including T

, (ii) PQ is the periodic queue, (iii) AQ

is the aperiodic queue. In our algorithm, we make

use of the following methods: (i) PQ.Sort() is a func-

tion that sorts the periodic queue according the the

DAG hierarchy and the Edge probability of the peri-

odic functions, (ii) AQ.Sort() is a function that sorts

the aperiodic queue according to the arrival time, (iii)

System.Run(F, T

exe

, freq, Voltage) is a function that

executes a function F during a time T

exe

and at the

speciﬁed frequency freq and voltage vol, (iv) Sys-

tem.Preempt() is a function that preempts a function

F and (v) AQ.Aperiodic Request() is a system call no-

tifying the scheduler about the arrival of a new ape-

riodic function in AQ. The output of this algorithm

is the next function to be executed with its estimated

scaled frequency f

scaled

and voltage V

scaled

. An ER-

ROR message is generated upon missing deadlines of

any periodic task. Our scheduling algorithm is de-

picted in the following:

Algorithm 1.

1: procedure I-CODESIGN SCHEDULING(VAR PQ: TAB-

PERIODIC, AQ: TAB-APERIODIC, TASKDAG: TREE, T:

TIME

2: for t = 0 to 2H do

3: if (t == 0) or (t mod P

PES

) == 0 then

4: C

PES

= MaxValue;

5: end if

6: if (AQ.Head! = null) then

7: System.Run(AQ.Head,C

PES

, f

max

)

8: else FrequencyScaling( PQ, AQ, f

scaled

)

9: System.Run(PQ.Head,ET

PQ.Head

, f

scaled

)

10: end if

11: if AQ.AperiodicRequest() then

12: System.Preempt()

13: System.Run(AQ.Head,C

PES

)

14: end if

15: end for

16: end procedure

Algorithm 2 implements the frequency scaling for

periodic tasks execution as follows: (i) U

is the

utilization of all periodic functions, and (ii) U

the utilization of aperiodic functions in the aperiodic

queue.

ICSOFT 2017 - 12th International Conference on Software Technologies

174

Algorithm 2.

1: procedure FREQUENCY SCALING(PQ: TAB-

PERIODIC, AQ: TAB-APERIODIC, VAR f

scaled

FREQUENCY)

2: U

= 0

3: for i = 0 → length(PQ) do

4: U

= U

+ PQ[i].C

/PQ[i].P

5: end for

6: if AQ! = null then

7: U

= C

8: else U

= 0

9: end if

10: U

= U

11: f

scaled

= min( f

, f

,.., f

max

)

12: U

≤ f

scaled

/ f

max

13: end procedure

The operating frequency selected is the lowest one

for which the modiﬁed schedulability test succeeds.

The voltage, of course, is changed to match the op-

erating frequency. This algorithm is called by Algo-

rithm 1 when a periodic function is speciﬁed for exe-

cution.

5.2 Example

We propose to apply the proposed algorithm on task

presented in ﬁgure 3. The task is composed of a

set of periodic function F= {F

, F

, .., F

} and ape-

riodic functions A= {A

, A

}. The output of I-

codesign methodologyapplied to T

are two partition-

ing clusters. The operating frequencies are f= {0.25,

0.5, 0.75, 1} Ghz.

0.5/10

0.4/8

0.7/9

0.8/12

0.1/6

0.3/12

0.2/5

1/7

1/13

1/9

1/13

Figure 3: Task graph T

Figure 4: Resulted Clusters after applying I-codesign to T

The ﬁnal clusters are presented in ﬁgure 4. We

propose to study the scheduling of cluster C1. The

real-time parameters of the periodic and aperiodic

functions are presented in Table-I and Table II.

Table-I describes the aperiodic task set with arrival

time and execution time. Table II describes the peri-

odic tasks proprieties including the defferable server.

Table 1: Aperiodic functions Set.

Function

Arrival Time

Execution

Time C

5 2

7 2

21 3

Table 2: Periodic functions Set.

Function

Priority

5 20 20 1

3 22 22 2

6 25 25 3

3 38 38 4

2 35 35 5

2 32 32 6

5 50 50 7

PES

2 5 5 1

In order to schedule the functions associated to the

cluster C1, the PQ and AQ are populated according to

the proposed priority deﬁnition and arrival time. For

this example, a high priority server is created with

an execution time of 2 time units and a period of 5

time units. At time= 0, the server’s execution time

is brought to its full capacity. This capacity is pre-

served until the ﬁrst aperiodic request occurs at time =

5 since there is no pending aperiodic function. Hence,

is executed. The frequency is scaled at the value

f= 0.75 Ghz. At time= 5, the periodic request occurs

to serve A

along with F

in the head of the periodic

queue. Clearly, A

is serviced at the maximum fre-

quency f= 1 Ghz until time= 7. F

and F

belong to the

same DAG level, hence the probability on the edges

connecting these functions with F

is assessed in or-

der to determine the next function to be executed at

time= 7. F

is serviced at a scaled frequency eaqual

to 0.75 Ghz since EdgeProba (F

)

∨

EdgeProba (F

At time= 10, the server’s execution time at priority 1

is brought to its full capacity and is used to provide

immediate service for A

at the maximum frequency

f= 1 Ghz. At time= 12, F

is serviced since there are

no periodic function with higher edge probability at

its DAG level at the frequency f= 0.75 Ghz followed

by F

at time= 18 at a scaled frequency of 0.5 Ghz. At

An Energy Aware Scheduling for Reconﬁgurable Heterogeneous Systems

175

time= 20, F

is serviced until time= 21 at a frequency

f= 0.5 Ghz when it is preempted in order to serve A

immediately at the maximum frequency f= 1 Ghz. at

time= 23, F

continues its execution at f= 0.75 Ghz.

Figure 5 illustrates the time-line scheduling of the ex-

ample as described above.

12 14 16

F1F5

12 14 16

Periodic Requests

Aperiodic Requests

Figure 5: Scheduling time-line of the cluster C1.

Table III shows the resulting schedule of the given

example task in table I and II.

Table 3: Defferable Server Schedule.

Time Released Pending f

scaled

PES

0 F

– 0.75 2

5 A

– 1 0

7 F

0.75 0

10 A

– 1 0

12 F

– 0.75 0

18 F

– 0.5 2

20 F

– 0.5 2

21 A

1 0

21 F

– 0.75 0

6 SIMULATION RESULTS

In a previous work (Ghribi et al., 2016b), we de-

veloped a co-design execution environment called

SPEX. It provides a toolbox that allows the creation

of a hardware/software system description accord-

ing to the proposed design models and that imple-

ments the I-codesign algorithms. It proposes a ﬂex-

ible task set generator for different scenarios and pur-

poses. The tool places the software speciﬁcation fol-

lowing several proposed design constraints as inclu-

sion/exclusion parameters, probabilistic execution of

the software tasks, available memory and energy on

the hardware units and real-time parameters. To eval-

uate the new scheduling algorithm several task sets

of different dimensions are generated. The generated

tasks are passed through SPEX and we obtain map-

ping scheme of the task set. We developed a new

simulation module that implements our scheduling al-

gorithm based on defferable server along with DVFS

technique. The simulator populates the periodic and

aperidoic queue, runs the speciﬁcation according to

function characteristics and generates estimations of

the total execution time and consumed energy.

In order to evaluate the proposed scheduling al-

gorithms, various random task sets are generated ac-

cording to the I-codesign modeling for probabilistic

reconﬁgurable task sets. These tasks are decomposed

into elementary functions and then characterized with

the different co-design constraints (probability, com-

munication costs, inclusion/exclusion). After apply-

ing the I-codesign algorithms, the resulting mapping

is passed through the scheduling simulator. The

scheduling results are compared to Earliest Deadline

First (EDF) algorithm and the Rate Monotonic al-

gorithm. Figures 6 and 7 present the performance

results of our scheduling algorithm applied to dif-

ferent task sets along with those of EDF and RM.

The comparison between the evaluated approaches

has demonstrated that the new I-codesign schedul-

ing algorithm offers better performance results par-

ticularly with large utilization factors and high num-

ber of nodes on the speciﬁcation DAGs. These en-

hancements are due to probabilistic estimation of the

communicated functions/behaviors that store depen-

dent tasks with high chances to be executed succes-

sively on same PEs. Simulation results show that this

contribution has many beneﬁts: (i) the energy con-

sumed during the system execution has been notice-

ably reduced and (ii) the global execution time has

been minimized. Another advantage of I-codesign is

its validation tests that includes real-time feasibility

which result in avoiding any system fail due to a lack

of resources.

7 CONCLUSIONS

In this work, an energy aware real-time scheduling al-

gorithm with Dynamic Voltage and Frequency Scal-

ing based on the Defferable Server has been pro-

posed and implemented for mixed task set. This

new scheduling algorithm is developed in order to en-

hance the I-codesign methodology. It considers the

trade-offs between the energy consumption and the

response time. It relies on simple constraints: the

DAG hierarchy and the probability of execution for

periodic functions. It makes use of DVFS technique

in order to reduce the energy consumption of the sys-

tem. Extensive simulation is carried out on our tasks

sets. The results showed that our proposed energy ef-

ﬁcient algorithm succeeds in reducing noticeably the

energy consumption with no degradation in respon-

siveness of aperiodic tasks.

ICSOFT 2017 - 12th International Conference on Software Technologies

176

0 0.2 0.4

0.6

0.8 1

Utilization

Task set I

New I-codesign

Old I-codesign

EDF algorithm

RM algorithm

0 0.2 0.4

0.6

0.8 1

Utilization

Task set II

New I-codesign

Old I-codesign

EDF algorithm

RM algorithm

0 0.2 0.4

0.6

0.8 1

Utilization

Task set III

New I-codesign

Old I-codesign

EDF algorithm

RM algorithm

Figure 6: Simulation Results for Energy Consumption.

0 0.2 0.4

0.6

0.8 1

100

150

Utilization

task set I

New I-codesign

Old I-codesign

EDF algorithm

RM algorithm

0 0.2 0.4

0.6

0.8 1

100

150

Utilization

task set II

New I-codesign

Old I-codesign

EDF algorithm

RM algorithm

0 0.2 0.4

0.6

0.8 1

100

150

Utilization

task set III

New I-codesign

Old I-codesign

EDF algorithm

RM algorithm

Figure 7: Simulation Results for Execution Time.

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