Behavioural Modelling of Digital Circuits in System Verilog using Grammatical Evolution

Conor Ryan, Michael Kwaku Tetteh, Douglas Mota Dias, Douglas Mota Dias

2020

Abstract

Digital circuit design is an immensely complex and time consuming task that has been aided greatly by the use of Hardware Description Languages and powerful digital circuit simulators that permit a designer to program at a much higher level of abstraction, similar to how software programmers now rarely use Assembly Language, and also to test their circuits before committing them to hardware. We introduce Automatic Design of Digital Circuits (ADDC), a system comprised of Grammatical Evolution (GE), System Verilog, a high level Hardware Description Language (HDL) and Icarus, a powerful, but freely available, digital circuit simulator. ADDC operates at a much higher level than previous digital circuit evolution due to the fact that System Verilog supports behavioural modelling through the use of high level constructs such as If-Then-Else, Case and Always procedural blocks. Not only are HDLs very expressive, but they are also far more understandable than circuit diagrams, so solutions produced by ADDC are quite interpretable by humans. ADDC is applied to three benchmark problems from the Digital Circuit Literature. We show that ADDC is successful on all three benchmarks and further demonstrate how the integration of simple knowledge, e.g. the separation of input and output wires, is feasible through the grammars, and can have a major impact on overall performance.

Paper Citation

in Harvard Style

Ryan C., Tetteh M. and Dias D. (2020). Behavioural Modelling of Digital Circuits in System Verilog using Grammatical Evolution. In Proceedings of the 12th International Joint Conference on Computational Intelligence (IJCCI 2020) - Volume 1: ECTA; ISBN 978-989-758-475-6, SciTePress, pages 28-39. DOI: 10.5220/0010066600280039

in Bibtex Style

@conference{ecta20,
author={Conor Ryan and Michael Kwaku Tetteh and Douglas Mota Dias},
title={Behavioural Modelling of Digital Circuits in System Verilog using Grammatical Evolution},
booktitle={Proceedings of the 12th International Joint Conference on Computational Intelligence (IJCCI 2020) - Volume 1: ECTA},
year={2020},
pages={28-39},
publisher={SciTePress},
organization={INSTICC},
doi={10.5220/0010066600280039},
isbn={978-989-758-475-6},
}

in EndNote Style

TY - CONF

JO - Proceedings of the 12th International Joint Conference on Computational Intelligence (IJCCI 2020) - Volume 1: ECTA
TI - Behavioural Modelling of Digital Circuits in System Verilog using Grammatical Evolution
SN - 978-989-758-475-6
AU - Ryan C.
AU - Tetteh M.
AU - Dias D.
PY - 2020
SP - 28
EP - 39
DO - 10.5220/0010066600280039
PB - SciTePress