Framework of Software Design Patterns for Energy-Aware Embedded

Systems

Marco Schaarschmidt

1 a

, Michael Uelschen

1 b

, Elke Pulverm

uller

and Clemens Westerkamp

Faculty of Engineering and Computer Science, University of Applied Sciences Osnabr

uck, Germany

Software Engineering Research Group, University of Osnabr

uck, Germany

Keywords:

Embedded Software Engineering, Embedded Systems, Software Design Pattern, Energy Efﬁciency, Power

Consumption, Internet of Things.

Abstract:

With the increasing size and complexity of embedded systems, the impact of software on energy consumption

is becoming more important. Previous research focused mainly on energy optimization at the hardware level.

However, little research has been carried out regarding energy optimization at the software design level. This

paper focuses on the software design level and addresses the gap between software and hardware design for

embedded systems. This is achieved by proposing a framework for software design patterns, which takes

aspects of power consumption and time behavior of the hardware level into account. We evaluate the expres-

siveness of the framework by applying it to well-known and novel design patterns. Furthermore, we introduce

a dimensionless numerical efﬁciency factor to make possible energy savings quantiﬁable.

1 INTRODUCTION

Due to advances in high-performance hardware and

new ﬁelds of applications, such as Internet of Things

(IoT) and Industrial Internet of Things (IIoT), the im-

portance of embedded systems is increasing. An em-

bedded system consists of a combination of hardware

and software components that interact with the sur-

rounding environment to achieve a speciﬁc task. Re-

quirements such as the access to energy resources,

power consumption and real-time behavior are be-

coming more important. At the same time, the com-

plexity of tasks accomplished by embedded systems

is constantly increasing, which results in a more pow-

erful and complex software. The program control

ﬂow and algorithms as well as the used hardware

components have a direct inﬂuence on the energy

efﬁciency of the system as one of the most critical

Non-Functional Requirements (NFR). For a battery-

operated system, the energy consumption is a chal-

lenging problem and often the bottleneck of a sys-

tem (Banerjee et al., 2016). Developers often have

a good understanding of the software application and

the hardware platform. However, when it comes to

power consumption and energy efﬁciency, they have

https://orcid.org/0000-0001-8260-5326

https://orcid.org/0000-0002-0841-6954

mostly limited knowledge and are often unsure of

how an application consumes energy and unaware of

best practices that reduce power consumption caused

by the application (Pang et al., 2016). Develop-

ing energy-efﬁcient software encompasses many parts

of software development. This includes not only

the optimized use of programming languages and

object-oriented programming (e.g. inheritance, poly-

morphism) but also the interaction between software

modules and hardware components (e.g. processor,

sensors). Signiﬁcant energy savings can be achieved

during the software design and architecture phase

(Tan et al., 2003). The authors also mentioned that it

is easier and less expensive to optimize the software

design of an embedded system in early stages rather

than trying to optimize the ﬁnal application. In the

context of software development, software patterns

are solutions for recurring problems and can be used

to overcome the complexity of applications. How-

ever, to the best of our knowledge, there is only lim-

ited work towards design patterns, which directly de-

scribe the effect on power consumption of a system.

To address the gap between the deﬁnition of software

design patterns and Energy-Aware hardware designs,

the following contributions are presented in this pa-

per:

• With respect to energy efﬁciency as a NFR, we

are addressing the gap between software and hard-

Schaarschmidt, M., Uelschen, M., Pulvermüller, E. and Westerkamp, C.

Framework of Software Design Patterns for Energy-Aware Embedded Systems.

DOI: 10.5220/0009351000620073

In Proceedings of the 15th International Conference on Evaluation of Novel Approaches to Software Engineering (ENASE 2020), pages 62-73

ISBN: 978-989-758-421-3

ware design by including power consumption and

timing behavior aspects of the underlying hard-

ware layer in the deﬁnition of software design pat-

terns.

• We describe a framework for Energy-Aware soft-

ware design patterns based on a proposal in (Ar-

moush, 2010).

• As part of the framework, we deﬁne the energy

balance EB

and the efﬁciency factor η

for each

Pattern P. EB

represents the difference between

the ability to save energy and additional energy

consumption. η

describes a quantitative estima-

tion of the efﬁciency of energy savings.

• To demonstrate the expressiveness of the frame-

work, we provide a catalog of Energy-Aware de-

sign patterns. These are enhanced by a uniform

description of temporal power consumption and

computing power characteristics, which helps de-

velopers to improve the energy efﬁciency of ap-

plications.

The remainder of this paper is organized as follows:

Section 2 describes research related to our approach.

An overview of power consumption analysis with a

power model description and software addressable

factors are presented in section 3. Section 4 contains

our proposed notation framework. Section 5 applies

our framework by presenting four Energy-Aware de-

sign patterns. A conclusion is provided in section 6.

2 RELATED WORK

Design patterns are a popular technique to document

proven best practices for recurring problems. The

work of (Gamma et al., 1994) (also known as Gang

of Four (GoF)) has become a widely accepted guid-

ance and includes common best practices for object-

oriented software development. The authors describe

pattern solutions for different types of problems in-

cluding structural and behavioral problems. Further-

more, the proposed representation includes ﬁelds ad-

dressing the context, structure and implementation.

The main drawback in common representation e.g.

(Douglass, 2011) is the lack of ﬁelds for NFRs, such

as energy efﬁciency or time behavior. (Armoush,

2010) extended those representations to consider the

NFRs in the pattern description. Their approach fo-

cuses strongly on aspects of safety-critical applica-

tions. Even if both hardware and software have to

fulﬁll NFRs, design patterns are strictly divided into

software- and hardware-based patterns. In case of en-

ergy efﬁciency, such a separation cannot be sustained

due to the close relationship between software and

hardware on this NFR. While this paper focuses on

Energy-Aware design patterns, other NFRs, like the

timing behavior of energy-efﬁcient applications, have

also been studied (Iyenghar and Pulvermueller, 2018).

Several authors consider the challenge of ana-

lyzing and improving energy efﬁciency in the pro-

cess of software development and for design pat-

terns. In (Litke et al., 2007) the authors explore

the power consumption and performance before and

after design patterns, such as Factory Method, Ob-

server or Adapter, are applied to an embedded sys-

tem. Other studies investigate the impact of design

patterns and object-oriented programming on energy

consumption. (Maleki et al., 2017) compare the im-

pact on power consumption for GoF design patterns.

(Feitosa et al., 2017) propose alternative pattern so-

lutions for GoF design patterns with a lower energy

consumption. (Noureddine and Rajan, 2015) improve

energy efﬁciency by optimizing design patterns auto-

matically at compile time. The described approaches

perform optimizations at the source code level and

on speciﬁc aspects of programming languages (e.g.

memory management, compiler optimization).

As shown in (Abdulsalam et al., 2014), changing

the programming languages and compiler settings can

heavily inﬂuence the performance as well as the en-

ergy efﬁciency of the software. Furthermore, (Bunse

and H

opfner, 2008) mentioned, that an optimization

during compile time is often inefﬁcient because an

optimal use of existing resources cannot really be pre-

dicted. This is especially the case for embedded sys-

tems in the IoT domain since the software is often

event-based and the behavior of the system depends

strongly on the environment in which the system is

employed. Additionally, all the optimizations regard-

ing programming languages and compilers are target-

ing the efﬁciency of the used processor. Since the

processor of an IoT device is not the main energy con-

sumer (Urard and Vu

cini

c, 2017), a more general ap-

proach is required. In (Reinfurt et al., 2017a; Reinfurt

et al., 2017b), a pattern framework as well as differ-

ent patterns for IoT devices on a more abstract level

were proposed. By postulating patterns which address

energy supply and energy harvesting approaches, the

authors took conditions of the environment and en-

ergy efﬁciency into account. The work is aimed at

complete IoT ecosystems (e.g. server systems and in-

frastructure) and only slightly addresses the behavior

of individual IoT nodes. However, to the best of our

knowledge, there is no approach that takes the close

connection between the software and hardware layer

for the deﬁnition of software design patterns into ac-

count.

Framework of Software Design Patterns for Energy-Aware Embedded Systems

3 POWER CONSUMPTION

This chapter contains a deﬁnition of energy consump-

tion and power models for embedded systems. It

also describes the inﬂuence of an application on the

power consumption P. Energy efﬁciency analysis and

esp. power consumption optimizations are challeng-

ing tasks. (Patterson and Hennessy, 2014) deﬁne a so-

called Power Wall for processors describing the cor-

relation between clock rate and the consumed power

Until the year 2004, both power consumption and

clock rate of devices have increased signiﬁcantly and

stagnated since. A practical power limit was reached

making a further reduction of power loss nearly im-

possible. The development of multi-core processors

was the next logical step. Consequently, the software

design became more dynamic and ﬂexible, but also

more complex and more difﬁcult to optimize. Fur-

thermore, energy efﬁciency cannot be analyzed in iso-

lation, because of its impact on other requirements of

the system. Modern embedded systems tend to have a

high complexity along with an increasing number of

different components like sensors and radio modules.

The total power consumption E

tot

of a system for a

given interval [0, T] is deﬁned as:

tot

P(t) dt (1)

To consider all components of a system, E

tot

in eq. 1

may be divided into two categories. One category en-

compasses complex components of a system, while

the other category encompasses simple components

of a system.

tot

∑

i=1

dyn

(t) + P

stat

(t)

| {z }

complex

∑

j=1

(t) · I

(t)

| {z }

simple

(2)

The ﬁrst part of eq. 2 deﬁnes the power consumption

for complex and clock-driven components with a dy-

namic part P

dyn

and a static part P

stat

. The second

part of eq. 2 addresses simple components which are

only manageable over the voltage V and electric cur-

rent I. The number of complex components is deﬁned

by n and the number of simple components by m re-

spectively. From a system point of view, a component

can be either deﬁned as a part of the System-on-a-

Chip (SoC) (e.g. analog-to-digital converter) or an

integrated part of the system (e.g. sensor, radio mod-

ule). In both cases, the application can be primar-

ily responsible for changes in the energy proﬁle of

the system and perform differently depending on the

combination of system components. Energy models

for complex and simple components are explained in

the following. Components (e.g. voltage regulators),

which are not directly affected by the application, are

not part of this paper.

3.1 Complex Components

The power P for complex components can be divided

in a static part P

stat

and dynamic part P

dyn

. P

stat

is typ-

ically described as the leakage current of transistors

(Kim et al., 2003). Since this is a typical behavior of

hardware components, from an application perspec-

tive, this can only be addressed by turning off func-

tion blocks of the component itself (known as Power

Gating). P

dyn

can be expressed as (Patterson and Hen-

nessy, 2014):

dyn

= nCV

f (3)

where n represents the number of transistors of a

given component, C the capacitance of a single tran-

sistor, V the supply voltage for the component and

f is the operating frequency. This energy model can

be used for processors or complex sensors with their

own CMOS logic. From an application perspective,

dyn

may be inﬂuenced by several parameters, which

is further explained in section 3.3.

3.2 Simple Components

The energy model for simple components used in

eq. 2 can be deﬁned as:

E =

V (t) · I(t) dt (4)

The time t, current I and voltage V as the main parts

of eq. 4 can be affected by the design of an appli-

cation and the algorithms running on an embedded

device. This model is used for simple components

which are not based on CMOS technology and are not

using clock generators. Examples are simple sensors

(e.g. photoresistor, temperature sensor) or infrared

and light diodes. From the application’s perspective,

the active time can be reduced by completing oper-

ations as efﬁciently and as fast as possible. The cur-

rent I can be reduced theoretically but may not always

be manageable by the application in practice. Further-

more, it is possible to optimize the program control

ﬂow, so that peripheral components are used less fre-

quently or switched off after being accessed.

3.3 Software Addressable Factors

This chapter addresses the gap between the hardware

and software design level, by including power con-

ENASE 2020 - 15th International Conference on Evaluation of Novel Approaches to Software Engineering

sumption and timing behavior aspects of the hard-

ware layer in the description of Energy-Aware soft-

ware design patterns. Eq. (2) describes the behavior

on a physical, hardware-related level, which causes

power consumption. The application can inﬂuence

the parameters presented below and therefore actively

reduce the consumption of a hardware system.

i) Time (t): Reduce the total time a system is running

by minimizing the workload, e.g., by using ef-

fective algorithms or optimizing the control ﬂow.

For some of those methods, hardware support is

needed (e.g. operation modes of the processor,

especially sleep modes).

ii) Capacity (n · C): Enable and disable components

and functional units when they are not actively

used. A policy for disabling and enabling com-

ponents may either be statically implemented be-

fore compilation or dynamically inﬂuenced dur-

ing runtime. This parameter also affects the static

power P

stat

from eq. (2).

iii) Voltage (V ): Increasing or decreasing the power

of the system or single components. This usually

requires support from the underlying hardware.

Another possibility is to turn off the power from

separated parts of the system. Depending on the

hardware layer, software developers do not always

have any control over those features (Oshana and

Kraeling, 2013).

iv) Frequency ( f ): Changing the operation frequency

of components (e.g. processor, sensors). This also

requires support from the hardware layer.

Well-known techniques like Dynamic Voltage Scal-

ing (DVS) (Lim et al., 2007), Dynamic Frequency

Scaling (DFS) (Pering et al., 1998) or Dynamic Volt-

age Frequency Scaling (DVFS) control voltage V and

frequency f to reduce consumption without turning

off the component. Such techniques are not or only

partially supported by typical low-costs and low-end

processors, like the ARM Cortex M family, which

are often used in battery-powered IoT devices. Such

hardware-based techniques cannot or only partially be

accessed from an application context. Even when pat-

terns can address energy-related problems by manag-

ing hardware accesses or using monitoring strategies,

they may cause additional overhead, e.g. power con-

sumption or execution time. This overhead also in-

creases the overall power consumption of the system

and therefore there exists a trade-off between the en-

ergy savings provided by the pattern and the energy

overhead of using the pattern. A detailed description

of the impact on energy consumption for each tem-

plate is part of the notation proposed in section 4.

4 NOTATION FRAMEWORK

This section describes our approach to create a frame-

work for a consistent documentation of software de-

sign patterns with an impact on energy efﬁciency.

Energy-aware Software Design Pattern Framework

Description

General

Information

Pattern Name

Other Names

Context

Preconditions

Realization

Strategy

Related Pattern

Impact on Non-

Functional Requirements

Energy Consumption

Execution Time/Latency

Modifiability

Development Costs

Problem

Abstract

Consequences (Optional)

Known Uses

Figure 1: Energy-Aware Design Pattern Framework.

The overall structure of this framework is shown in

ﬁgure 1. This approach is derived from the basic con-

cept described in (Armoush, 2010) and enhanced by

taking energy efﬁciency into account. Both solutions

consider the Execution Time as another closely related

NFR which also includes the impact on real-time re-

quirements. The template in ﬁgure 1 is divided into

three main parts: General Information, Description

and Impact on Non-Functional Requirements.

4.1 General Information

This part of the framework describes all meta infor-

mation, including the following elements:

• Pattern Name: A unique and meaningful name

that identiﬁes the pattern.

• Other Names: If exists, other well-known names

of the pattern or names of similar patterns realiz-

ing the basic concept.

• Strategy: Each pattern can address at least one of

the four main factors Time, Capacity, Voltage and

Frequency, proposed in the previous section 3.3.

• Related Patterns: If available, names of other pat-

terns, which are related to this pattern.

• Known Uses: A description of known uses in-

cluding other domains (e.g. electrical engineer-

ing) and existing products using the concept of

this pattern successfully.

4.2 Description

This section of a template contains the deﬁnition as

well as information of the basic pattern idea. The pre-

sented structure is based on the GoF pattern descrip-

tion (Gamma et al., 1994) and contains the following

elements:

Framework of Software Design Patterns for Energy-Aware Embedded Systems

• Abstract: A short description of the pattern to pro-

vide a ﬁrst overview.

• Context: Description of the situation to which this

pattern may be applied.

• Preconditions: Conditions that must be fulﬁlled in

order to apply this pattern. Conditions include re-

quirements and properties of the underlying hard-

ware system architecture.

• Problem: Description of the addressed problem

expressed as a question to describe the character-

istics of the speciﬁc problem.

• Realization: A detailed description of the pattern

including a graphical structure representation (if

applicable) as well as an overview of the individ-

ual elements and relations. A description of the

implementation and techniques while implement-

ing the design pattern can be included.

In typical software pattern descriptions (cf. section 2),

Uniﬁed Modeling Language (UML) diagrams like

structure, class and object diagrams are often used as

graphical representations. Depending on the type of

pattern (cf. section 3.3), some other UML represen-

tations like timing, activity and sequence diagrams as

well as statecharts may be used to deﬁne aspects of

the implementation.

4.3 Impact on NFR

This section describes the impact on NFRs like power

consumption as well as the impact on other energy-

related NFRs like execution time and latency. Ad-

ditionally, other consequences that are not energy-

related (e.g. development costs, modiﬁability) can

also be mentioned in this section.

• Power Consumption: For a uniﬁed description of

the impact on power consumption, we introduce

the energy balance EB

. A higher value of EB

means greater possible savings. Furthermore, we

deﬁne the efﬁciency factor η

to enable a quanti-

tative evaluation of the efﬁciency of energy sav-

ings (effort-saving ratio). η

= 1 means a pattern

saves energy without additional effort. A pattern

that does save energy results in η

= 0.

• Execution Time/Latency: Describes the impact of

a pattern on the execution time. In addition, laten-

cies caused by the pattern can be listed.

• Consequences: Drawbacks and side-effects with a

focus on the behavior and control ﬂow of the soft-

ware and system are considered. Also required

adaptations by the software developer as well as

additional hardware requirements are mentioned.

5 PATTERN CATALOG

In this section, we demonstrate our approach on four

selected Energy-Aware design patterns. Section 5.1–

5.3 describe well-known design patterns, while sec-

tion 5.4 presents a novel design pattern. Each descrip-

tion includes a power-timing diagram showing the be-

havior of the pattern related to the power consump-

tion, computation power and execution time. Based

on this diagram, the patterns are evaluated with the

proposed efﬁciency factor η

5.1 Pattern: Energy-Aware Sampling

In this section, the Energy-Aware Sampling (EAS)

pattern is described.

5.1.1 General Information

Other Names: Adaptive Sampling (Shu et al., 2017).

Strategy: This pattern inﬂuences the time an embed-

ded system (e.g. processor and sensor) is operating

in an active state. By lowering the sampling rate, the

component (e.g. sensor) can be set inactive for longer

periods and the processor can go into a (deep) sleep

mode. Increasing the sampling rate increases the

power consumption of the component due to a longer

active period. Depending on the strategy, a processor

can be in a low power or active state during sampling

of the component.

Related Pattern: Cost-Aware Sampling, where

the sampling rate is adapted according to energy

consumption, memory size and communication

bandwidth. Quality of Service Based Sampling

where the performance of the transmission network

affects the sampling rate. (Mi

skowicz, 2016)

Known Uses: In (Shu et al., 2017), a dynamically

adapting sampling frequency is used to save 30.66%

of the system’s battery energy during a three months

monitoring period.

5.1.2 Description

Abstract: According to (Tobola et al., 2015), the

sample rate of a system has a large impact on the

power consumption of the system. As the main

problem, this pattern addresses the acquisition of

sensor data in an Energy-Aware way by using a

sampling rate, which ﬁts the relevant frequencies

to extract all the necessary information. Following

the Nyquist-Shannon sampling theorem (Landau,

1967), the signal can be reconstructed perfectly, if the

ENASE 2020 - 15th International Conference on Evaluation of Novel Approaches to Software Engineering

maximum frequency f

max

is known and the sampling

rate results in f

sample

> 2 · f

max

. This represents the

lowest limit for the reduction of the sampling rate.

Context: Use EAS in situations where signal prop-

erties are known (e.g. maximum frequencies) and

algorithms can handle varying sample rates.

Preconditions: This pattern is highly suitable for

periodic systems (e.g. constant sampling rates)

without interrupts. At least one component, typically

a sensor with capabilities to adjust the sampling rate,

is required. In addition, when using this pattern, the

characteristics of the signal must be well known.

Problem: How can a system optimize the overall

energy consumption by adopting the sample rate of

single components (e.g. sensors) individually?

Realization: The pattern interferes only slightly with

the existing application and can be implemented

rapidly. The ﬁrst step is to change the period dura-

tion for the sensor reading. In the case of a static ad-

justment, this ideally takes place when the program is

executed the ﬁrst time. If the sampling interval is sup-

posed to vary during run-time, further software com-

ponents may need to be adapted.

5.1.3 Impact on Non-Functional Requirements

Figure 2 shows the power-related behavior of the pro-

cessor for the basic deﬁnition of EAS without consid-

ering peripheral devices and sensors.













Energy Savings





















No Pattern

Pattern Applied

Figure 2: EAS Power Characteristics.

Energy Consumption: In the upper part of ﬁgure 2, the

power consumption for the sleep mode is deﬁned as

and for the normal mode as P

. In the lower part,

represents the computing power during normal

mode. The power (duty) cycle for such applications

is deﬁned as:

D =

c = t

−t

T = t

−t

(5)

with c as the duration when the processor/system is in

normal mode and T as the overall period. Applying

this pattern, a new period T

> T is deﬁned and leads

to a new relaxed power cycle D

, which is deﬁned as:

= t

−t

(6)

∆P

= P

− P

(7)

The energy balance EB

can be calculated using the

eq. (6)–(7):

= E

normal

− E

relaxed

= (D ·∆P

) − (D

· ∆P

)

= ∆P

(D − D

)

(8)

There is a linear relationship between relaxing the

duty cycle and energy savings. Additional effort

(power and computing power) is not required which

leads to an efﬁciency factor η

= 1. When taking

other devices into account, eq. (8) needs to be

extended, which is beyond the scope of this paper.

Execution Time/Latency: Reducing the duty cycle

has a positive effect on the execution time of the

software application. Furthermore, periodic latencies,

e.g. waiting for measured values of a sensor, can be

reduced this way.

Consequences: By applying this pattern the number

of total data points and possibly the accuracy of the

sampled signal decreases due to the reduced sampling

rate.

5.2 Pattern: Race-To-Sleep

In this section, the Race-To-Sleep pattern is de-

scribed.

5.2.1 General Information

Other Names: Race-To-Idle, Race-To-Halt, Race-To-

Zero, Race-To-Black.

Strategy: This pattern inﬂuences the timing behavior

(cf. section 3.3) of a system. It uses the highest

possible operating frequency to compute the work-

load by the application as fast as possible. After the

associated task is ﬁnished, the processor switches

to a low-power state to save energy. If a multi-core

environment is available, the application can be split

and executed on different processor cores, which also

Framework of Software Design Patterns for Energy-Aware Embedded Systems

addresses the timing behavior of an application.

Related Pattern: The concept of this pattern can be

extended for multi-core platforms. An application,

can (partially) beneﬁt from parallel processing, which

can reduce the execution time signiﬁcantly and the

system is able to enter a low-power state earlier

(Rossi et al., 2017).

Known Uses: Mentioned as Race-To-Idle, this pattern

is used for speed scaling in (Albers and Antoniadis,

2014). A multi-core scenario is described in (Rossi

et al., 2017).

5.2.2 Description

Abstract: This pattern has a signiﬁcant inﬂuence

on the behavior of the software by addressing the

dynamic part P

dyn

and the static part P

stat

as described

in eq 2. To achieve energy efﬁciency, the highest

possible operating frequency of a core can be used

and additionally the application can be split and

executed on different processor cores. The imple-

mentation type varies with processor characteristics

and the application structure. Computing-intensive

applications can proﬁt especially from this pattern.

Context: Use the Race-To-Sleep pattern in situations

where applications are computationally intensive or

consist of computational intensive parts.

Preconditions: The processor must be able to change

the frequency during runtime. If a multi-core system

for parallel processing is used, software developers

must ensure, that the software can be parallelized and

does not induct bottlenecks due to serialization.

Problem: How can an application be computed as

fast as possible while also maximizing the time a

system operates in a low-power mode?

Realization: Based on the features and capabilities of

the processor, this pattern can be applied by adjusting

the frequency and by splitting the workload to differ-

ent cores. Frequency alteration has to be supported

by the underlying operating system. Otherwise, this

functionality has to be implemented by using software

libraries (drivers and middleware) and advanced algo-

rithms to predict the need for a higher frequency. This

can be achieved by measuring the current workload or

using provided performance counters of the proces-

sor. For a dual-core processor, the concept of splitting

the workload is illustrated in ﬁgure 3. A fork-join ap-

proach can be used to split the workload and speed-up

the computation.

















Fork

Join

Figure 3: Race-To-Sleep in Multi-Core Environment.

The workload is divided and processed on different

cores starting at time t

. After the last core has ﬁn-

ished the workload at time t

, the results are merged

in a join process. The increase in computation power

results from additional processor cores.

5.2.3 Impact on Non-Functional Requirements

The impact on NFRs described in this section is ex-

emplarily explained for a parallel computation using

a dual-core processor, as shown in ﬁgure 4.





















Energy Savings

Add. Energy













No Pattern

Pattern Applied

Figure 4: Race-To-Sleep Power Characteristics.

Energy Consumption: The upper part of ﬁgure 4

shows the temporal behavior of the pattern where P

represents the power consumption with P

, P

for

consumptions at sleep, normal and race mode. For a

dual-core processor, the normal mode is deﬁned as the

mode where only one processor core is active while

in race mode both cores are used. When a single-core

processor is considered, the race mode is equivalent

to an increased frequency of the processor. CP de-

scribes the computing power with CP

as the comput-

ing power for the normal mode and CP

for the race

mode. The timestamps t

, t

indicate the start and end-

point of race mode while t

indicates the beginning of

sleep mode. Applying this design pattern, the appli-

cation enters race mode at t

. The computing power

is increased and as a consequence also the power con-

sumption. During this mode, the application ﬁnishes

it’s computation and switches to the sleep mode at t

To describe this behavior, the following declarations

and assumptions are required:

ENASE 2020 - 15th International Conference on Evaluation of Novel Approaches to Software Engineering

∆P

= P

− P

∆P

= P

− P

(9)

∆t

= t

−t

∆t

= t

−t

(10)

save

= ∆P

· ∆t

add

= ∆P

· ∆t

(11)

∆P

< ∆P

∆t

≥ ∆t

(12)

∆P

= q

< 1

∆t

= q

≥ 1 (13)

is deﬁned as the quotient between the power con-

sumption of the race and normal mode and q

as the

quotient between the duration of the race and normal

mode. The energy balance EB

can be calculated us-

ing eq. (9–12) with:

= E

save

− E

add

= ∆P

· ∆t

− ∆P

· ∆t

= ∆P

· ∆t

(1 − q

)

(14)

is positive if the energy savings are larger than

the additional energy, which is required to ﬁnish

the computing earlier. We deﬁne η

= (1 − q

Considering the MPC8641 multi-core system

(Svennebring et al., 2009), the additional energy con-

sumption is 30% higher compared to the MPC8641

running as single-core, so that q

= 0.3. When

choosing q

= 1.2, we get η

= 0.74.

Execution Time/Latency: Since this pattern ensures

faster processing of the application, it has a positive

inﬂuence on the execution time. The execution and

end time of the application can vary and are difﬁcult

to predict, as the pattern dynamically changes the

computing power during run-time.

Consequences: Because some peripherals (e.g.

timers) depend on the clock rate of the SoC, it must

be ensured, that they are synchronized with the new

clock-rate and, for example, that intervals are rede-

ﬁned if the adjustment of the frequency is achieved

without the support of the operating system. Fur-

thermore, to lower the execution time, an application

also has to be designed in such a way, that ideally no

blocking accesses and waiting periods are used. If an

application blocks the process (e.g. waiting for re-

sults) or cannot be parallelized, the effect of this pat-

tern is reduced.

5.3 Pattern: Mirroring

In this section, the Mirroring pattern is described.

5.3.1 General Information

Other Names: -

Strategy: This pattern inﬂuences the timing behavior

of the application (cf. section 3.3), by modifying how

long certain parts of the processor stay in speciﬁc

operation modes.

Related Pattern: -

Known Uses: ARM uses a technology called

big.LITTLE for their heterogeneous multi-processor

architectures to assign threads either to a high-power

or energy efﬁciency core, depending on the expected

computational intensity (Yu et al., 2013). This archi-

tecture may consist of an ARM Cortex A53 and Cor-

tex A57 (dual quad-core).

5.3.2 Description

Abstract: The Mirroring pattern migrates tasks

between processor cores with different levels of

power consumption.

Context: Developing energy-efﬁcient software for

embedded systems in situations, where the underly-

ing hardware contains a multi-core architecture and a

task’s execution environment can be controlled dy-

namically. This pattern can also be used on processor

architectures, where cores have different instruction

set architectures and programming languages.

Preconditions: A typical conﬁguration consists

of a fast, high-power processor core alongside a

slower, energy-efﬁcient core. The different cores of a

processor must have the ability to communicate with

each other (e.g. signaling).

Problem: How can individual cores of a multi-core

system be dynamically switched on and off by

software at runtime to increase energy efﬁciency

without stopping the application software?

Realization: Figure 5 shows a software model of the

Mirroring pattern. The elements of the pattern pre-

sented in ﬁgure 5 are:

• TaskGroup: Consists of a Task and a MirrorTask

implementation. A Task is actively executed after

initialization. A MirrorTask is a passive copy of a

Task, allocated to another core and only powered

on when a migration is executed.

• CoreGroup: Abstraction of cores for a processor

with controlling mechanisms as well as parame-

ters for NFRs.

• CoreControl: Manages CoreGroups and controls

Framework of Software Design Patterns for Energy-Aware Embedded Systems

uses

Assignment

Strategy

EnergyRules

CoreControl

CoreGroup

MigrationUnit

TaskGroup

defines

controls

1..n

runs on

1 1..n

Figure 5: Structure of the Mirroring Pattern.

communication between the tasks. The class con-

sists of the following three main elements:

– Strategy: Manages the execution and associa-

tion of cores and tasks. Deﬁnes the order in

which tasks are migrated and cores powered.

– EnergyRules: Parameters for measuring the

load of the cores. Rules based on processor reg-

isters, performance counter or other techniques

can be used to control cores and tasks.

– MigrationUnit: Task management and switch-

ing strategies as well as power management

functions. It provides functions to instruct the

cores and perform migrations.

The concept of this pattern can be applied to dif-

ferent processor architectures. If an architecture

and operation system support technologies like ARM

big.LITTLE, tasks can be switched between cores

without the need to extend parts of the software de-

sign. Otherwise, a management layer which controls

the tasks has to be developed, as presented in ﬁgure 5.

5.3.3 Impact on Non-Functional Requirements

The impact of using the Mirroring pattern on various

energy-related parameters is described below.

Energy Consumption: The purpose of this pattern is

to optimize the energy efﬁciency of the system by

dynamically controlling the different cores of a pro-

cessor. The impact on consumption depends on how

the cores are controlled. Figure 6 shows an exam-

ple of this pattern applied on a system with a dual-

core processor consisting of an energy-efﬁcient core

and a high-power core. The upper part shows the

power consumption P of the processor, where P

rep-

resents power consumption while both cores are in

sleep mode, P

shows the power consumption of the

energy-efﬁcient core, P

shows the power consump-

tion of the high-power core and P

the consumption

of both cores. The levels of computing power CP





























Energy Savings

Add. Energy

















No Pattern

Pattern Applied

Figure 6: Mirroring Power Characteristics.

can be described as CP

for the energy-efﬁcient core,

for the high-power core and CP

as the computing

power for both cores. The switching (mirroring) of a

task starts at t

. In addition to the running high-power

core, the low-power core is started. The application

moves relevant computing tasks from the high-power

to the low-power core. At t

, the high-power core

is put into sleep mode. Between t

and t

, the sys-

tem is utilizing the low-power core. At t

the mirror-

ing starts again by shifting the computing tasks to the

large core. For calculating the energy balance EB

we deﬁne:

∆t

= t

−t

∆t

= t

−t

∆t

= t

−t

(15)

∆P

= P

− P

∆P

= P

− P

(16)

∆P

= q

< 1

∆t

= q

< 1 (17)

and assume that ∆t

= ∆t

. Using eq. (15)–(17),

can be calculated:

= E

save

− E

add

= ∆P

· ∆t

− 2 · ∆P

· ∆t

= ∆P

· ∆t

(1 − 2 · q

)

(18)

For this pattern, the efﬁciency factor is speciﬁed as

= (1 − 2 · q

). For example: if q

= 0.125 and

= 0.1, we get the efﬁciency factor η

= 0.975.

The power consumption highly depends on the

application as well as processor characteristics and

needs to be considered in detail. Each change of

a state (e.g. go-to-sleep and wake-up) consumes

energy (e.g. load and unload of capacitance), which

has to be considered in the application design (Urard

and Vu

cini

c, 2017).

Execution Time/Latency: There are two different im-

pacts on the execution time when using this pattern.

The ﬁrst impact is the time related to the overhead

during the execution of CoreControl. The second

ENASE 2020 - 15th International Conference on Evaluation of Novel Approaches to Software Engineering

impact is caused by the processor conﬁgurations. If a

task is moved between two differently clocked cores,

the execution time can be shortened or extended.

Consequences: This pattern can be modiﬁed to con-

trol N cores and assign M different tasks to the N

cores (N, M ∈ N). If the cores have the same archi-

tecture and compilers for the same programming lan-

guage, the development costs are low. If source code

for a Task has to be ported from e.g. C++ to Assem-

bler or if multiple cores with different compilers and

programming languages are used, the development

costs will increase because of the N different software

versions of the same task. CoreControl is the manag-

ing instance, so it must be executed on a core that is

either permanently active or switched off last. To get

the best energy balance, this core is typically the most

energy-efﬁcient core.

5.4 Pattern: PowerMonitor

In this section, we describe the PowerMonitor pat-

tern in detail, whose general idea was introduced in

(Uelschen et al., 2019).

5.4.1 General Information

Other Names:-

Strategy: This pattern reduces the active time of a

peripheral device as well as the overall capacity of

the system by automatically disabling all peripheral

devices and interfaces which are no longer in use or

requested by any part of the application.

Related Pattern: -

Known Uses: At the block level of integrated circuit

design (hardware layer), this technique is known as

power-gating. (Jiang et al., 2005)

5.4.2 Description

Abstract: The PowerMonitor pattern considers the

power consumption properties of both the SoC

itself and external peripheral devices. The access of

external peripheral and interfaces (e.g. I

C or SPI)

are managed by a single instance. The centralized

approach allows a deep knowledge of the devices

and it can disable devices and change their power

modes dynamically when they are temporarily not

needed. This also includes interfaces with one or

more devices connected to it.

Context: Use the PowerMonitor pattern when an

application has to access peripheral interfaces and

devices periodically. This pattern is also suitable

when a centralized and ﬁne-grained hardware access

control has to be achieved.

Preconditions: This application requires physical

access of all interfaces (e.g. I

C or SPI) and the

application must have the direct or indirect capability

to disable and enable external devices like sensors

and actuators as well as clocks of functional units.

Problem: How may a ﬁne-grained dynamic power

consumption strategy be implemented, which runs

application code while only enabling peripheral

devices on request? Additionally, how can conﬂicts

between sleep modes (e.g. preventing software from

being executed) and use cases (e.g. performing

continuous tasks) be addressed?

Realization: The reference implementation for this

pattern follows a C++17 template meta-programming

approach and provides an abstract and type-safe in-

terface. Only the PowerMonitor interacts with hard-

ware devices so that every other instance can use the

provided functions and does not have to implement

the hardware access itself, which could be a repetitive

and time-consuming process.

5.4.3 Impact on Non-Functional Requirements

Figure 7 sketches the power characteristics of the

PowerMonitor pattern.





















Energy Savings

















No Pattern

Pattern Applied





Figure 7: PowerMonitor Power Characteristics.

Energy Consumption: The computing power (lower

part of ﬁgure 7) is not affected by this pattern and

remains constant at level CP

. We assume that the

considered functional unit and the peripheral device

are disabled before t

. The power consumption of this

state is denoted as P

.To describe the behavior, the

following declarations are required:

Framework of Software Design Patterns for Energy-Aware Embedded Systems

T = t

−t

∆P

= P

− P

∆P

= P

− P

(19)

∆t

= t

−t

∆t

= t

−t

∆t

= t

−t

(20)

In order to access devices, the PowerMonitor enables

at ﬁrst the functional unit (e.g. I

C) beginning at t

Afterwards at t

, the peripheral device (sensor con-

nected via I

C) gets enabled. During ∆t

, the appli-

cation can access the device without loss of function-

ality. The power consumption level is P

. After uti-

lization, the application dynamically disables the ex-

ternal device at ﬁrst and the functional unit of the SoC

afterwards. The power consumption drops back to the

previous level P

. The energy savings of the pattern

depends on the power consumption of the SoC’s func-

tional unit ∆P

and the external device ∆P

. EB

can be calculated using eq. (19)–(20):

normal

= T · ∆P

monitor

= (∆t

+ ∆t

) · ∆P

| {z }

≈0

+∆t

· ∆P

= E

save

= E

normal

− E

monitor

= ∆P

· (T − ∆t

)

(21)

The ﬁrst part of E

monitor

can be ignored since the

fast enabling of functional units usually takes only

a few clock cycles. Because the basic concept of

this pattern does not require additional energy, the

efﬁciency factor η

= 1.

Execution Time/Latency: Switching devices on and

off adds latencies which are caused by the software

itself and the affected hardware components. To

achieve a clear and simple description of the basic

concept of this pattern shown in ﬁgure 7, additional

latencies are not considered. Those latencies depend

on the characteristics of the hardware layer and

cannot be generalized.

Consequences: For each new interface (e.g. I

C) and

device (e.g. sensor) used in the system, the Power-

Monitor needs to be extended which can increase the

development time and required hardware resources

(e.g. memory) of the application.

6 CONCLUSION

In this paper, we presented a novel approach to in-

clude power consumption in the deﬁnition of soft-

ware design patterns for embedded systems. First,

we have shown how the software can inﬂuence the

power consumption of an embedded system. Next, a

framework to describe Energy-Aware software design

patterns is proposed. The approach modiﬁes and ex-

tends well-known pattern descriptions with attributes

related to the power consumption. We used the pro-

posed pattern framework to uniformly document four

design patterns with effects on the energy efﬁciency

of a system. Software developers can use the frame-

work to express software design patterns affecting the

energy consumption. Based on a power-timing dia-

gram, which is presented for all pattern descriptions,

we introduce the efﬁciency factor, a dimensionless

numerical value in order to make possible energy sav-

ings quantiﬁable. The efﬁciency factor describes the

trade-off between energy savings and the energy over-

head of a pattern. It can be a helpful tool to compare

the energy efﬁciency on different systems using the

same pattern. However, the efﬁciency factor is not

suitable for comparing the efﬁciency of energy sav-

ings between different patterns.

Future work following the current results includes

an extension of a pattern catalog by systematically de-

scribing more patterns using the framework. This can

lead to the design of a reference catalog to point out

the advantages of each pattern for a speciﬁc problem

domain. Another part of the future work includes an

analysis of the effect on energy consumption for use

cases where more than one pattern is used at the same

time.

ACKNOWLEDGEMENTS

This work was partially funded by the German Fed-

eral Ministry of Economics and Technology (Bun-

desministeriums fuer Wirtschaft und Technologie-

BMWi) within the project ”Holistic Model Driven

Development for embedded systems in consideration

of diverse hardware architectures” (HolMES). The

authors are responsible for the contents of this pub-

lication.

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