the axes. Moreover, the movement of one probe may
cross a very tall component, i.e., a “no-fly” zone.
Furthermore, a path can violate other physical con-
straints, as probes should not collide and they can-
not change their relative position along the x-axis.
These situations can arise because the optimizer has
not been able to find a better schedule for all the tests
or simply because it did not foresee, or care about,
low-level details (i.e., the actual trajectories) of the
planning process. In addition, when performing the
test, a movement may be invalid because of the ac-
tual positioning of the board on the conveyance sys-
tem, and such eventuality cannot be foreseen. Finally,
there are cases in which the test engineer may manu-
ally ask for a specific test to be performed, i.e., added,
at run-time.
To reduce the above problems, we propose an ap-
proach to detect invalid movements due to path inter-
section and we correct the trajectories on-the-fly. In
our approach, when a problem is detected, a heuristic
strategy adds new steps to the plan. In other words,
independently from the reasons that make the step
s
i+1
illegal, we add extra steps
b
s
j
to the overall probe
path, to make the whole sequence valid again, i.e.,
{s
i
,
b
s
0
, . . . ,
b
s
n
, s
i+1
}. The additional steps
b
s
j
do not
specify any tests, but provide a legal trajectory for the
probes, i.e.,
b
s
j
= (
b
p
j
, ∅). Each new step, implies a
new set of probe movements which we define to be
safe and collision free. Determining the additional
steps is complex and the process may iterate, lead-
ing to a solution in which new movements are added
over and over again to make previous steps valid.
As the cost of the test is mainly related to its time
length, the time necessary to locate additional points
should be carefully traded-off with the time required
to follow the new path. Furthermore, as modern test
devices have up to 8 probes, we coordinate their con-
current movements and we recur to a parallel imple-
mentation of our techniques to be as fast as possi-
ble. We show, that our algorithms can exploit parallel
multi-core devices (CPUs) and many-core modern ar-
chitecture (GPUs). Experimental results show up-to
a 10x speedup factor using our parallel CPU-based
and up-to a 70x speedup factor using our many-core
GPU-based application.
The paper is organized as follows. Section 2 re-
ports some considerations on related works and Sec-
tion 3 formally describes our testing environment. Af-
ter that, Section 4 illustrates our methodology and
Section 5 includes our experimental evidence. Fi-
nally, Section 6 concludes the paper with few sum-
marizing remarks and some hints on future works.
2 RELATED WORKS
Components that are soldered during the assembly
phase, to hold their correct position, can suffer from
defects, and PCBs need to be thoroughly tested. Un-
fortunately, PCBs are becoming extremely complex
and many boards have significantly more components
and solder joints today than just a few years ago.
Many research papers on board-assembly testing fo-
cus on boundary scan test, processor-controlled test,
or other powered digital testing techniques. These
works mostly ignore that circuits can incur damage
that could have been avoided by executing a non-
powered test first.
(Radev and Shirvaikar, 2006) investigate the pos-
sibility of enhancing a flying probe tester with an au-
tomated optical inspection module. Following face
recognition strategies, the authors first perform train-
ing using several images of the PCB. Then, to achieve
a wide range of defect detection and decrease inspec-
tion times, they verify their method with different
level of noise, occlusion, position shift, rotation, and
lighting variation.
(Soh Ying Seah et al., 2009) combine two test
platforms, namely flying-probe in-circuit test and
load board verification on an automatic test equip-
ment.
(Hiratsuka et al., 2010) present an early work on
an in-circuit testers with two flying probes. The au-
thors apply an extension of the Traveling Salesman
Problem algorithm formulated as an integer linear
programming problem to minimize the total time of
the inspection.
(van Schaaijk et al., 2018) describe a software tool
that automatically generates in-circuit tests based on
the product design files, without requiring probe ac-
cess on every net. The software also indicates in
which parts of the board the fault coverage is not max-
imal, and hence where extra probe access will im-
prove the test quality.
(Bonaria et al., 2019a) detail a technique to op-
timize the flying probes positioning in a SPEA 4080
test equipment. In order to minimize the test time, the
authors concentrate on re-arranging the sequence of
tests, considering the tester capabilities, the board lay-
out, and several constraints coming from the environ-
ment and the customer. The authors finally compare
the new algorithm with the old one, i.e., the FP2012,
whose performances were sub-optimal with a high
number of test blocks and test points.
(Jurj et al., 2020) design a hybrid sensor-less tester
by combining the features of flying probe testing
and the capabilities of a coordinate measuring ma-
chine. The experimental results show that the pro-
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