et al., 2012, Figure 5) to verify that both outputs
from garbled circuit are the same. All benchmarks
without downloading boolean circuits were ran in a
single-threaded on an Intel i5 CPU 2.3GHz and 16GB
2133MHz LPDDR3 of RAM in the 13-inch (2018)
macbook pro.
Table 1: Basic information of circuits: f
mkg
, f
aux
, and f
ckd
.
f
mkg
f
aux
f
ckd
Total number of gates 847,420 796,827 507,581
Total number of wires 850,558 799,676 510,463
Table 2: Time consuming for running 20 samples.
2P-MKG 2P-CKD
Fast time 7.181s 2.688s
Slow time 7.748s 2.839s
Avg time 7.374s ± 0.14s 2.739s ± 0.04s
The bit-length of seed = 512, n = 33, and Paillier public key = 2048;
The number of base OT = 128; The half-gates scheme uses the
Hash function
[
MMO
E
(ref. (Guo et al., 2020, Section 7.3))
with the ideal cipher AES-128.
5 CONCLUSION AND
DISCUSSION
The proposed protocols comply with all BIP32 regu-
lations. We also provided a security proof in the hy-
brid model using simulation-based methods and ex-
perimental data. Theoretically, there will be risk in
leaking bits while using DualEx protocol since we
considered the worst scenario without any restric-
tions on g in the security proof. The leaking risk
can be potentially overcame by utilizing garbled cir-
cuit schemes against malicious adversaries such as
authenticated Garbling method.
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