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Designing of ALU Block for RISC-V-Based Processor Core with Low
Power
K. Madhava Rao
a
, T. Vasudeava Reddy and Uthej
B. V. Raju institute of Technology, BVRIT, Narsapur, Marsapur, Medak, India
Keywords: RISC-V Architecture, Parallel-Prefix Adders, Kogge-Stone Adder, Galois-Field Multiplier, Approximate
Computing, Instruction Sets.
Abstract: We are in an era of technology where the speed, power, and area of the VLSI chip are the three extremely
crucial factors. Adders and multipliers form key components in a variety of arithmetic and logical processes.
For binary addition, Parallel Prefix Adder (PPA) is an effective and useful circuit that has evolved. Fast
Kogge-Stone Adder (KSA) is Parallel Prefix Adder that is used for making fast addition operations. A Galois
Filed Multiplier (GFM) is also developed for making fast operations that work on shift operation technique.
The objective of the research is to integrate FKS and GFM that accommodate superior systems to improvise
a performance. Both of these modules are integrated into an ALU block of the RISC V processor. The design
has been implemented for a 32-Bit sequence. and the entire design was implemented in Xilinx ISE and Open
Lane toolset.
1 INTRODUCTION
In an emerging digital world, systems like
microprocessors and data processing jobs like
filtering, object recognition, convolution, image and
video compression, modulation, and so on, the
addition and multiplication of the binary values (say
two) is amongst the most fundamental and important
aspects of the arithmetic logic unit (ALU). The binary
adders and multipliers in these systems are crucial
aspects of an ALU. The requirements referring to an
adder in VLSI systems need to be quick and reliable
in terms of speed, area, and power. The adder design
architecture is primarily responsible for performing
operations. Because RISC V is an open-sourced
definition of an Instruction Set Architecture, the
architecture considered here is RISC architecture
(ISA). In contrast to most other ISA designs.
Nowadays, we do not want to waste our crucial
time doing a single task the same goes for the
processors. Nobody would want to have an electronic
device with a slow processor, but how are adders and
multipliers related to processors? The answer is
simple – the better the adder and multiplier design
techniques the faster the processor works. We
a
https://orcid.org/0000-0003-3115-6385
measure the speed of processors by the time it takes
them to complete a task; the time it takes the
processors to complete a task is normally equal to the
overall propagation delay in the circuit. The
circuit/processor becomes slower as the propagation
delay increases, and the opposite is also true. With the
preceding argument, we may also conclude that 'the
fewer the propagation delays, the faster the
circuit/processor, and vice versa. The data transfer
rate of the carry chain is a key concern for binary
addition. As the input bit or operand size rises with
the length of the carry chain. The Modern PPA
architecture consists of Pre-Processing (Felzmann et
al 2020), Carry Look-Ahead, and Post-Processing
parts utilized to prevent the problem of Carry chain
propagation. In binary addition of digital systems,
these adders are used to build the most efficient
circuit (Shilpa et al 2016) (here we used an ALU
block based on RISC architecture). The performance
and latency of these adders are mostly determined by
total levels in carry generation. To reduce
propagation latency, we added two modules to the
CPU's ALU block: the Kogge-stone adder and the
Galois field multiplier.
Rao, K., Reddy, T. and Uthej, .
Designing of ALU Block for RISC-V-Based Processor Core with Low Power.
DOI: 10.5220/0012559700003739
Paper published under CC license (CC BY-NC-ND 4.0)
In Proceedings of the 1st International Conference on Artificial Intelligence for Internet of Things: Accelerating Innovation in Industry and Consumer Electronics (AI4IoT 2023), pages 71-76
ISBN: 978-989-758-661-3
Proceedings Copyright © 2024 by SCITEPRESS – Science and Technology Publications, Lda.
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