Meta-Heuristic Optimization of Transistor Sizing in CMOS Digital Designs

Prashanth H. C., Madhav Rao

2023

Abstract

Designing new custom standard cells or digital circuits using automated optimization is challenging considering the large design space, performance trade-offs and continuous technology progression. Besides, a comprehensive study and analysis of different algorithms applied towards optimizing higher-order custom digital circuit design is imperative. In this work, 28 Transistor (28T) 1-bit full-adder (FA) is designed and investigated for six optimization algorithms, including particle-swarm-optimization (PSO), evolutionary strategy (ES), genetic algorithm (GA), differential evolution (DE), NSGA-II, and NSGA-III. The algorithms are evaluated and benchmarked, considering diversity of candidate solutions, monotonicity of fitness convergence, and capability to reach the best solution when initiated with a randomly seeded solution. This work establishes that GA produces best-fit circuits among all the single-objective algorithms. ES and GA exhibit good designspace exploration, unlike PSO and DE, which are influenced by local optima. NSGA-II, and NSGA-III are preferred when the objective is to give equal importance to the targeted parameters. The extensive evaluation of the algorithms in this work will aid in adopting an effective strategy for optimizing custom circuits for the specified objective parameters.

Paper Citation

in Harvard Style

H. C. P. and Rao M. (2023). Meta-Heuristic Optimization of Transistor Sizing in CMOS Digital Designs. In Proceedings of the 15th International Joint Conference on Computational Intelligence - Volume 1: ECTA; ISBN 978-989-758-674-3, SciTePress, pages 278-287. DOI: 10.5220/0012198400003595

in Bibtex Style

@conference{ecta23,
author={Prashanth H. C. and Madhav Rao},
title={Meta-Heuristic Optimization of Transistor Sizing in CMOS Digital Designs},
booktitle={Proceedings of the 15th International Joint Conference on Computational Intelligence - Volume 1: ECTA},
year={2023},
pages={278-287},
publisher={SciTePress},
organization={INSTICC},
doi={10.5220/0012198400003595},
isbn={978-989-758-674-3},
}

in EndNote Style

TY - CONF

JO - Proceedings of the 15th International Joint Conference on Computational Intelligence - Volume 1: ECTA
TI - Meta-Heuristic Optimization of Transistor Sizing in CMOS Digital Designs
SN - 978-989-758-674-3
AU - H. C. P.
AU - Rao M.
PY - 2023
SP - 278
EP - 287
DO - 10.5220/0012198400003595
PB - SciTePress