HIGH THROUGHPUT MEMORY-EFFICIENT VLSI DESIGNS FOR STRUCTURED LDPC DECODING

Hrishikesh Sharma, Subhasis Das, Rewati Raman Raut, Sachin Patkar

2011

Abstract

Low-density Parity Check(LDPC) codes have been in focus of intense research in Error-correction Coding in recent years. High throughput decoder design for them has been a big challenge for these codes. In this paper, we report the first scalable VLSI decoder design based on projective geometry (PG) structure of LDPC codes. The design is based on memory-efficient communication primitives known as perfect access sequences. A high-throughput variation of above design achieves a throughput of 620 Mbps, much higher than what communication standards require. The corresponding fully-parallel VLSI architecture was implemented on Xilinx LX110T FPGA, as well as on 90-nm SAED EDK90 CORE Cell Library from Synposys. We find that PG-based graphs indeed offer an exciting way of parallelizing this computation, and many others in future.

References

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Paper Citation


in Harvard Style

Sharma H., Das S., Raman Raut R. and Patkar S. (2011). HIGH THROUGHPUT MEMORY-EFFICIENT VLSI DESIGNS FOR STRUCTURED LDPC DECODING . In Proceedings of the 1st International Conference on Pervasive and Embedded Computing and Communication Systems - Volume 1: PECCS, ISBN 978-989-8425-48-5, pages 518-521. DOI: 10.5220/0003366305180521


in Bibtex Style

@conference{peccs11,
author={Hrishikesh Sharma and Subhasis Das and Rewati Raman Raut and Sachin Patkar},
title={HIGH THROUGHPUT MEMORY-EFFICIENT VLSI DESIGNS FOR STRUCTURED LDPC DECODING},
booktitle={Proceedings of the 1st International Conference on Pervasive and Embedded Computing and Communication Systems - Volume 1: PECCS,},
year={2011},
pages={518-521},
publisher={SciTePress},
organization={INSTICC},
doi={10.5220/0003366305180521},
isbn={978-989-8425-48-5},
}


in EndNote Style

TY - CONF
JO - Proceedings of the 1st International Conference on Pervasive and Embedded Computing and Communication Systems - Volume 1: PECCS,
TI - HIGH THROUGHPUT MEMORY-EFFICIENT VLSI DESIGNS FOR STRUCTURED LDPC DECODING
SN - 978-989-8425-48-5
AU - Sharma H.
AU - Das S.
AU - Raman Raut R.
AU - Patkar S.
PY - 2011
SP - 518
EP - 521
DO - 10.5220/0003366305180521