AER SPIKE-PROCESSING FILTER SIMULATOR - Implementation of an AER Simulator based on Cellular Automata

Manuel Rivas-Perez, A. Linares-Barranco, A. Jimenez-Fernandez, A. Civit, G. Jimenez

2011

Abstract

Spike-based systems are neuro-inspired circuits implementations traditionally used for sensory systems or sensor signal processing. Address-Event-Representation (AER) is a neuromorphic communication protocol for transferring asynchronous events between VLSI spike-based chips. These neuro-inspired implementations allow developing complex, multilayer, multichip neuromorphic systems and have been used to design sensor chips, such as retinas and cochlea, processing chips, e.g. filters, and learning chips. Furthermore, Cellular Automata (CA) is a bio-inspired processing model for problem solving. This approach divides the processing synchronous cells which change their states at the same time in order to get the solution. This paper presents a software simulator able to gather several spike-based elements into the same workspace in order to test a CA architecture based on AER before a hardware implementation. Furthermore this simulator produces VHDL for testing the AER-CA into the FPGA of the USB-AER AER-tool.

References

  1. Von Neumann, J., 1966. The Theory of Self-reproducing Automata, A. Burks, ed., Univ. of Illinois Press, Urbana, IL.
  2. Von Neumann, J., 1966. The Theory of Self-reproducing Automata, A. Burks, ed., Univ. of Illinois Press, Urbana, IL.
  3. Burks, A., 1970. Essays on Cellular Automata. Univ. Illinois Press.
  4. Burks, A., 1970. Essays on Cellular Automata. Univ. Illinois Press.
  5. Pesavento, U., 1995. An implementation of von Neumann's self-reproducing machine. Artificial Life, Vol. 2, pp. 337-354.
  6. Pesavento, U., 1995. An implementation of von Neumann's self-reproducing machine. Artificial Life, Vol. 2, pp. 337-354.
  7. Sivilotti, M., 1991. Wiring Considerations in analog VLSI Systems with Application to Field-Programmable Networks, Ph.D. Thesis, California Institute of Technology, Pasadena CA.
  8. Sivilotti, M., 1991. Wiring Considerations in analog VLSI Systems with Application to Field-Programmable Networks, Ph.D. Thesis, California Institute of Technology, Pasadena CA.
  9. Boahen, K. A., 1998. Communicating Neuronal Ensembles between Neuromorphic Chips. Neuromorphic Systems. Kluwer Academic Publishers, Boston.
  10. Boahen, K. A., 1998. Communicating Neuronal Ensembles between Neuromorphic Chips. Neuromorphic Systems. Kluwer Academic Publishers, Boston.
  11. Serrano-Gotarredona, R., Oster, M., Lichtsteiner, P., Linares-Barranco, A., Paz-Vicente, R., GómezRodríguez, F., et al., 2009. CAVIAR: A 45k-neuron, 5M-synapse AER Hardware Sensory-ProcessingLearning-Actuating System for High-Speed Visual Object Recognition and Tracking, IEEE Trans. on Neural Networks, Vol. 20. Núm. 9. Pag. 1417-1438.
  12. Serrano-Gotarredona, R., Oster, M., Lichtsteiner, P., Linares-Barranco, A., Paz-Vicente, R., GómezRodríguez, F., et al., 2009. CAVIAR: A 45k-neuron, 5M-synapse AER Hardware Sensory-ProcessingLearning-Actuating System for High-Speed Visual Object Recognition and Tracking, IEEE Trans. on Neural Networks, Vol. 20. Núm. 9. Pag. 1417-1438.
  13. Cohen, A., et al., 2006. Report to the National Science Foundation: Workshop on Neuromorphic Engineering, Telluride, Colorado, USA, June-July 2006.
  14. Cohen, A., et al., 2006. Report to the National Science Foundation: Workshop on Neuromorphic Engineering, Telluride, Colorado, USA, June-July 2006.
  15. CNEW, 2011. The 2011 Cognitive Neuromorphic Engineering Workshop.
  16. CNEW, 2011. The 2011 Cognitive Neuromorphic Engineering Workshop.
  17. Serrano-Gotarredona, R., et al., 2006. A Neuromorphic Cortical-Layer Microchip for Spike-Based Event Processing Vision Systems. IEEE T Circuits SystemsI, Vol. 53, No 12, pp. 2548-2566, Dec-2006.
  18. Serrano-Gotarredona, R., et al., 2006. A Neuromorphic Cortical-Layer Microchip for Spike-Based Event Processing Vision Systems. IEEE T Circuits SystemsI, Vol. 53, No 12, pp. 2548-2566, Dec-2006.
  19. Linares-Barranco, A., Paz, R., Gómez-Rodríguez, F., Jiménez, A., Rivas-Perez, M., Jiménez, G., and Civit A., 2009. FPGA Implementations comparison of Neuro-Cortical inspired Convolution Processors for Spiking Systems. Lecture Notes in Computer Science Vol. 5517, pp.97-105, 2009.
  20. Linares-Barranco, A., Paz, R., Gómez-Rodríguez, F., Jiménez, A., Rivas-Perez, M., Jiménez, G., and Civit A., 2009. FPGA Implementations comparison of Neuro-Cortical inspired Convolution Processors for Spiking Systems. Lecture Notes in Computer Science Vol. 5517, pp.97-105, 2009.
  21. Rivas-Perez, M., Linares-Barranco, A., Cerda, J., Ferrando, N., Jimenez, G., Civit, A., 2010. Visual Spike-based convolution processing with a Cellular Automata Architecture. The 2010 International Joint Conference on Neural Networks (IJCNN). DOI: 10.1109/IJCNN.2010.5596924.
  22. Rivas-Perez, M., Linares-Barranco, A., Cerda, J., Ferrando, N., Jimenez, G., Civit, A., 2010. Visual Spike-based convolution processing with a Cellular Automata Architecture. The 2010 International Joint Conference on Neural Networks (IJCNN). DOI: 10.1109/IJCNN.2010.5596924.
  23. Farabet, C., Poulet, C., Han, J. Y., LeCun, Y., 2009. CNP: An FPGA-based Processor for Convolutional Networks. International Conference on Field Programmable Logic and Applications. FPL 2009.
  24. Farabet, C., Poulet, C., Han, J. Y., LeCun, Y., 2009. CNP: An FPGA-based Processor for Convolutional Networks. International Conference on Field Programmable Logic and Applications. FPL 2009.
  25. Farrig, N., Mamalet, F., Roux, S., Yang, F., Paindavoine, M., 2008. Design of a Real-Time Face Detection Parallel Architecture Using High-Level Synthesis. Hindawi Publishing Corporation. EURASIP Journal on Embedded Systems. Vol. 2008, id 938256.
  26. Farrig, N., Mamalet, F., Roux, S., Yang, F., Paindavoine, M., 2008. Design of a Real-Time Face Detection Parallel Architecture Using High-Level Synthesis. Hindawi Publishing Corporation. EURASIP Journal on Embedded Systems. Vol. 2008, id 938256.
  27. LeCun, Y., Bottou, L., Bengio, Y., & Haffner, P. Gradient-based learning applied to document recognition. Proceedings of the IEEE, 86, 2278-2324.
  28. LeCun, Y., Bottou, L., Bengio, Y., & Haffner, P. Gradient-based learning applied to document recognition. Proceedings of the IEEE, 86, 2278-2324.
  29. Huang, F.-J., LeCun, Y., 2006. Large-scale learning with svm and convolutional nets for generic object categorization. In Proc. Computer Vision and Pattern Recognition Conference (CVPR'06). IEEE.
  30. Huang, F.-J., LeCun, Y., 2006. Large-scale learning with svm and convolutional nets for generic object categorization. In Proc. Computer Vision and Pattern Recognition Conference (CVPR'06). IEEE.
  31. Ranzato, M., Huang, F., Boureau, Y., & LeCun, Y., 2007. Unsupervised learning of invariant feature hierarchies with applications to object recognition. In Proc. Computer Vision and Pattern Recognition Conference (CVPR'07). IEEE Press.
  32. Ranzato, M., Huang, F., Boureau, Y., & LeCun, Y., 2007. Unsupervised learning of invariant feature hierarchies with applications to object recognition. In Proc. Computer Vision and Pattern Recognition Conference (CVPR'07). IEEE Press.
  33. Jarrett, K., Kavukcuoglu, K., Ranzato, M., & LeCun, Y., 2009. What is the best multi-stage architecture for object recognition? In Proc. International Conference on Computer Vision (ICCV'09). IEEE.
  34. Jarrett, K., Kavukcuoglu, K., Ranzato, M., & LeCun, Y., 2009. What is the best multi-stage architecture for object recognition? In Proc. International Conference on Computer Vision (ICCV'09). IEEE.
  35. Osadchy, R., Miller, M., & LeCun, Y., 2004. Synergistic face detection and pose estimation with energy-based model. In Advances in Neural Information Processing Systems (NIPS 2004). MIT Press.
  36. Osadchy, R., Miller, M., & LeCun, Y., 2004. Synergistic face detection and pose estimation with energy-based model. In Advances in Neural Information Processing Systems (NIPS 2004). MIT Press.
  37. Hadsell, R., Sermanet, P., Scoffier, M., Erkan, A., Kavackuoglu, K., Muller, U., & LeCun, 2009. Y. Learning long-range vision for autonomous off-road driving. Journal of Field Robotics, 26 , 120-144.
  38. Hadsell, R., Sermanet, P., Scoffier, M., Erkan, A., Kavackuoglu, K., Muller, U., & LeCun, 2009. Y. Learning long-range vision for autonomous off-road driving. Journal of Field Robotics, 26 , 120-144.
  39. Farabet, C., Poulet, C., Han, J. Y., LeCun, Y., 2009. CNP: an FPGA-based processor for Convolutional Networks. International Conference on Field Programmable Logic and Applications (FPL). pp 32- 37. DOI: 10.1109/FPL.2009.5272559.
  40. Farabet, C., Poulet, C., Han, J. Y., LeCun, Y., 2009. CNP: an FPGA-based processor for Convolutional Networks. International Conference on Field Programmable Logic and Applications (FPL). pp 32- 37. DOI: 10.1109/FPL.2009.5272559.
  41. Gomez-Rodriguez, F., Paz, R., Linares-Barranco, A., Rivas M., 2006. AER tools for Communications and Debugging. Proceedings of the IEEE ISCAS 2006.
  42. Gomez-Rodriguez, F., Paz, R., Linares-Barranco, A., Rivas M., 2006. AER tools for Communications and Debugging. Proceedings of the IEEE ISCAS 2006.
  43. Chan, V., Liu, S. C., van Schaik, A., 2007. AER EAR: A Matched Silicon Cochlea Pair with Address-EventRepresentation Interface. IEEE Trans. Circuits and Systems-I. Vol. 54, No 1. pp. 48-59. Jan-2007.
  44. Chan, V., Liu, S. C., van Schaik, A., 2007. AER EAR: A Matched Silicon Cochlea Pair with Address-EventRepresentation Interface. IEEE Trans. Circuits and Systems-I. Vol. 54, No 1. pp. 48-59. Jan-2007.
  45. Serrano-Gotarredona, R. et al., 2006. A Neuromorphic Cortical-Layer Microchip for Spike-Based Event Processing Vision Systems. IEEE T Circuits SystemsI, Vol. 53, No 12, pp. 2548-2566, Dec-2006.
  46. Serrano-Gotarredona, R. et al., 2006. A Neuromorphic Cortical-Layer Microchip for Spike-Based Event Processing Vision Systems. IEEE T Circuits SystemsI, Vol. 53, No 12, pp. 2548-2566, Dec-2006.
  47. Costas-Santos, J., Serrano-Gotarredona, T., SerranoGotarredona R. and Linares-Barranco, B., 2007. A Spatial Contrast Retina with On-chip Calibration for Neuromorphic Spike-Based AER Vision Systems. IEEE Trans. Circuits and Systems-I, vol. 54, No. 7, pp. 1444-1458, July 2007
  48. Costas-Santos, J., Serrano-Gotarredona, T., SerranoGotarredona R. and Linares-Barranco, B., 2007. A Spatial Contrast Retina with On-chip Calibration for Neuromorphic Spike-Based AER Vision Systems. IEEE Trans. Circuits and Systems-I, vol. 54, No. 7, pp. 1444-1458, July 2007
  49. Hafliger, P., 2007. Adaptive WTA with an Analog VLSI Neuromorphic Learning Chip. IEEE Transactions on Neural Networks, vol. 18, No 2, pp. 551-572. 2007.
  50. Hafliger, P., 2007. Adaptive WTA with an Analog VLSI Neuromorphic Learning Chip. IEEE Transactions on Neural Networks, vol. 18, No 2, pp. 551-572. 2007.
  51. Indiveri, G., Chicca, E., Douglas, R., 2006. A VLSI Array of Low-Power Spiking Neurons and Bistables Synapses with Spike-Timig Dependant Plasticity. IEEE Transactions on Neural Networks, vol. 17, No 1, pp 211-221. Jan-2006.
  52. Indiveri, G., Chicca, E., Douglas, R., 2006. A VLSI Array of Low-Power Spiking Neurons and Bistables Synapses with Spike-Timig Dependant Plasticity. IEEE Transactions on Neural Networks, vol. 17, No 1, pp 211-221. Jan-2006.
Download


Paper Citation


in Harvard Style

Rivas-Perez M., Linares-Barranco A., Jimenez-Fernandez A., Civit A. and Jimenez G. (2011). AER SPIKE-PROCESSING FILTER SIMULATOR - Implementation of an AER Simulator based on Cellular Automata . In Proceedings of the International Conference on Signal Processing and Multimedia Applications - Volume 1: SIGMAP, (ICETE 2011) ISBN 978-989-8425-72-0, pages 91-96. DOI: 10.5220/0003525900910096


in Harvard Style

Rivas-Perez M., Linares-Barranco A., Jimenez-Fernandez A., Civit A. and Jimenez G. (2011). AER SPIKE-PROCESSING FILTER SIMULATOR - Implementation of an AER Simulator based on Cellular Automata . In Proceedings of the International Conference on Signal Processing and Multimedia Applications - Volume 1: SIGMAP, (ICETE 2011) ISBN 978-989-8425-72-0, pages 91-96. DOI: 10.5220/0003525900910096


in Bibtex Style

@conference{sigmap11,
author={Manuel Rivas-Perez and A. Linares-Barranco and A. Jimenez-Fernandez and A. Civit and G. Jimenez},
title={AER SPIKE-PROCESSING FILTER SIMULATOR - Implementation of an AER Simulator based on Cellular Automata},
booktitle={Proceedings of the International Conference on Signal Processing and Multimedia Applications - Volume 1: SIGMAP, (ICETE 2011)},
year={2011},
pages={91-96},
publisher={SciTePress},
organization={INSTICC},
doi={10.5220/0003525900910096},
isbn={978-989-8425-72-0},
}


in Bibtex Style

@conference{sigmap11,
author={Manuel Rivas-Perez and A. Linares-Barranco and A. Jimenez-Fernandez and A. Civit and G. Jimenez},
title={AER SPIKE-PROCESSING FILTER SIMULATOR - Implementation of an AER Simulator based on Cellular Automata},
booktitle={Proceedings of the International Conference on Signal Processing and Multimedia Applications - Volume 1: SIGMAP, (ICETE 2011)},
year={2011},
pages={91-96},
publisher={SciTePress},
organization={INSTICC},
doi={10.5220/0003525900910096},
isbn={978-989-8425-72-0},
}


in EndNote Style

TY - CONF
JO - Proceedings of the International Conference on Signal Processing and Multimedia Applications - Volume 1: SIGMAP, (ICETE 2011)
TI - AER SPIKE-PROCESSING FILTER SIMULATOR - Implementation of an AER Simulator based on Cellular Automata
SN - 978-989-8425-72-0
AU - Rivas-Perez M.
AU - Linares-Barranco A.
AU - Jimenez-Fernandez A.
AU - Civit A.
AU - Jimenez G.
PY - 2011
SP - 91
EP - 96
DO - 10.5220/0003525900910096


in EndNote Style

TY - CONF
JO - Proceedings of the International Conference on Signal Processing and Multimedia Applications - Volume 1: SIGMAP, (ICETE 2011)
TI - AER SPIKE-PROCESSING FILTER SIMULATOR - Implementation of an AER Simulator based on Cellular Automata
SN - 978-989-8425-72-0
AU - Rivas-Perez M.
AU - Linares-Barranco A.
AU - Jimenez-Fernandez A.
AU - Civit A.
AU - Jimenez G.
PY - 2011
SP - 91
EP - 96
DO - 10.5220/0003525900910096