A CASE STUDY OF ENERGY-EFFICIENT LOOP INSTRUCTION CACHE DESIGN FOR EMBEDDED MULTITASKING SYSTEMS

Ji Gu, Tohru Ishihara

2012

Abstract

Microprocessors increasingly execute multiple tasks in step with the increasing complexity of modern embedded applications. Shared by multiple tasks, conventional on-chip L1 instruction cache (I-cache) usually suffers a high cache miss ratio due to inter/intra task interferences and is the most energy-consuming component of the processor chip. This paper presents a power-efficient loop instruction cache design for multitasking embedded applications, which is a two-fold technique that can significantly reduce the L1 I-cache accesses for energy saving and reduce the I-cache misses caused by task interference. Experiments on a case study show that our scheme reduces energy consumption in the I-cache hierarchy by 36.5% and I-cache misses can be reduced from 6.0% to 18.3%, depending on the frequency of context switch in the multitasking system.

References

  1. Burger, D. C. and Austin, T. M. (1997). The simplescalar tool set, version 2.0. Technical Report CS-TR-1997- 1342, Department of Computer Science, University of Wisconsin, Madison.
  2. Dally, W. J., Balfour, J., Black-Shaffer, D., Chen, J., Harting, R. C., Parikh, V., Park, J., and Sheffield, D. (2008). Efficient embedded computing. IEEE Computer, 41(7):27-32.
  3. Gauthier, L., Ishihara, T., Takase, H., Tomiyama, H., and Takada, H. (2010). Minimizing inter-task interferences in scratch-pad memory usage for reducing the energy consumption of multi-task systems. In Proceedings of the 2010 international conference on Compilers, architectures and synthesis for embedded systems (CASES'10) , pages 157-166.
  4. Gu, J. and Guo, H. (2010). Enabling large decoded instruction loop caching for energy-aware embedded processors. In Proceedings of the 2010 international conference on Compilers, architectures and synthesis for embedded systems (CASES'10) , pages 247-256.
  5. Guthaus, M. R., Ringenberg, J. S., Ernst, D., Austin, T. M., Mudge, T., and Brown, R. B. (2001). Mibench: A free, commercially representative embedded benchmark suite. In IEEE 4th Annual Workshop on Workload Characterization, pages 83-94.
  6. Malik, A., Moyer, B., and Cermak, D. (2000). A low power unified cache architecture providing power and performance flexibility. In Proceedings of the 2000 International Symposium on Low Power Electronics and Design (ISLPED'00) , pages 241-243.
  7. Pan, D. Z. (2009). Low power design and challenges in nanometer multicore era. In IEEE CAS Melbourne and Victoria University, Invited Talks, August 20, 2009.
  8. Paul, M. and Petrov, P. (2011). Dynamically adaptive icache partitioning for energy-efficient embedded multitasking. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 19(11):2067-2080.
  9. Reddy, R. and Petrov, P. (2010). Cache partitioning for energy-efficient and interference-free embedded multitasking. ACM Transactions on Embedded Computing Systems (TECS), 9(3):16:1-16:35.
  10. Scott, J., Lee, L. H., Arends, J., and Moyer, B. (1998). Designing the low-power m-core architecture. In International Sympsium on Computer Architecture Power Driven Microarchitecture Workshop, pages 145-150.
  11. Tang, W., Gupta, R., and Nicolau, A. (2002). Power savings in embedded processors through decode filer cache. In Proceedings of the Conference on Design, Automation and Test in Europe (DATE'02) , pages 443-448.
  12. Thoziyoor, S., Muralimanohar, N., Ahn, J. H., and Jouppi, N. P. (2008). CACTI: An integrated cache and memory access time, cycle time, area, leakage, and dynamic power model. Technical Report HPL-2008-20, HP Laboratories.
  13. Yang, C.-L. and Lee, C.-H. (2004). Hotspot cache: Joint temporal and spatial locality exploitation for icache energy reduction. In Proceedings of the International Symposium on Low Power Electronics and Design, pages 114-119.
  14. Zhang, C., Vahid, F., Yang, J., and Najjar, W. (2005). A way-halting cache for low-energy high-performance systems. ACM Transactions on Architecture and Code Optimization (TACO), 2(1):34-54.
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Paper Citation


in Harvard Style

Gu J. and Ishihara T. (2012). A CASE STUDY OF ENERGY-EFFICIENT LOOP INSTRUCTION CACHE DESIGN FOR EMBEDDED MULTITASKING SYSTEMS . In Proceedings of the 1st International Conference on Smart Grids and Green IT Systems - Volume 1: SMARTGREENS, ISBN 978-989-8565-09-9, pages 197-202. DOI: 10.5220/0003951001970202


in Bibtex Style

@conference{smartgreens12,
author={Ji Gu and Tohru Ishihara},
title={A CASE STUDY OF ENERGY-EFFICIENT LOOP INSTRUCTION CACHE DESIGN FOR EMBEDDED MULTITASKING SYSTEMS},
booktitle={Proceedings of the 1st International Conference on Smart Grids and Green IT Systems - Volume 1: SMARTGREENS,},
year={2012},
pages={197-202},
publisher={SciTePress},
organization={INSTICC},
doi={10.5220/0003951001970202},
isbn={978-989-8565-09-9},
}


in EndNote Style

TY - CONF
JO - Proceedings of the 1st International Conference on Smart Grids and Green IT Systems - Volume 1: SMARTGREENS,
TI - A CASE STUDY OF ENERGY-EFFICIENT LOOP INSTRUCTION CACHE DESIGN FOR EMBEDDED MULTITASKING SYSTEMS
SN - 978-989-8565-09-9
AU - Gu J.
AU - Ishihara T.
PY - 2012
SP - 197
EP - 202
DO - 10.5220/0003951001970202