A Buffer Cache Scheme Considering Both DRAM/PRAM Hybrid Main Memory and Flash Memory Storages

Soohyun Yang, Yeonseung Ryu

2013

Abstract

As the power dissipation has become one of the critical design challenges in a mobile environment, non-volatile memories such as PRAM and flash memory will be widely used in the next generation mobile computers. In this paper, we proposed an efficient buffer cache scheme considering the write limitation of PRAM for hybrid main memory as well as the erase-before-write limitation of flash memory for storage device. The goal of proposed scheme is to minimize the number of write operations on PRAM as well as the number of erase operations on flash memory. We showed through trace-driven simulation that proposed scheme outperforms legacy buffer cache schemes.

Paper Citation

in Harvard Style

Yang S. and Ryu Y. (2013). A Buffer Cache Scheme Considering Both DRAM/PRAM Hybrid Main Memory and Flash Memory Storages.In Proceedings of the 3rd International Conference on Pervasive Embedded Computing and Communication Systems - Volume 1: PECCS, ISBN 978-989-8565-43-3, pages 76-79. DOI: 10.5220/0004337200760079

in Bibtex Style

@conference{peccs13,
author={Soohyun Yang and Yeonseung Ryu},
title={A Buffer Cache Scheme Considering Both DRAM/PRAM Hybrid Main Memory and Flash Memory Storages},
booktitle={Proceedings of the 3rd International Conference on Pervasive Embedded Computing and Communication Systems - Volume 1: PECCS,},
year={2013},
pages={76-79},
publisher={SciTePress},
organization={INSTICC},
doi={10.5220/0004337200760079},
isbn={978-989-8565-43-3},
}

in EndNote Style

TY - CONF

JO - Proceedings of the 3rd International Conference on Pervasive Embedded Computing and Communication Systems - Volume 1: PECCS,
TI - A Buffer Cache Scheme Considering Both DRAM/PRAM Hybrid Main Memory and Flash Memory Storages
SN - 978-989-8565-43-3
AU - Yang S.
AU - Ryu Y.
PY - 2013
SP - 76
EP - 79
DO - 10.5220/0004337200760079