High-Speed Pipelined FPGA Implementation of a Robust Steganographic Scheme for Secure Data Communication Systems

Salah Harb, M. Ahmad, M. Swamy

2024

Abstract

In this paper, we introduce a high-speed and area-efficient hardware design for a novel modulus-based image steganographic scheme, specifically targeting constrained-area steganographic embedded systems. The proposed modulus-based image steganography scheme enhances both image quality and embedding rate while ensuring resilience against PVD histogram analysis, salt-and-pepper noise, and RS analysis attack. The hardware architecture incorporates pipelined registers placed to guarantee balanced-execution paths among computing components. A memory-less finite state machine model is developed to efficiently control the instructions for the steganographic operations. Employing a hardware-software co-design approach, the proposed hardware design is realized as an IP core on the AMD Xilinx Zynq-7000 APSoC platform. It processes concealing operations in just 13 clock cycles, utilizes 148 slices, and operates at 290 MHz. This results in a remarkable throughput of 2.32 Gbps. The hardware design demonstrates significant improvements in speed, resource utilization, and throughput compared to recent steganographic hardware implementations, making it ideal for resource-constrained, real-time applications ranging from secure embedded communication to advanced IoT data protection.

Paper Citation

in Harvard Style

Harb S., Ahmad M. and Swamy M. (2024). High-Speed Pipelined FPGA Implementation of a Robust Steganographic Scheme for Secure Data Communication Systems. In Proceedings of the 21st International Conference on Security and Cryptography - Volume 1: SECRYPT; ISBN 978-989-758-709-2, SciTePress, pages 397-406. DOI: 10.5220/0012716700003767

in Bibtex Style

@conference{secrypt24,
author={Salah Harb and M. Ahmad and M. Swamy},
title={High-Speed Pipelined FPGA Implementation of a Robust Steganographic Scheme for Secure Data Communication Systems},
booktitle={Proceedings of the 21st International Conference on Security and Cryptography - Volume 1: SECRYPT},
year={2024},
pages={397-406},
publisher={SciTePress},
organization={INSTICC},
doi={10.5220/0012716700003767},
isbn={978-989-758-709-2},
}

in EndNote Style

TY - CONF

JO - Proceedings of the 21st International Conference on Security and Cryptography - Volume 1: SECRYPT
TI - High-Speed Pipelined FPGA Implementation of a Robust Steganographic Scheme for Secure Data Communication Systems
SN - 978-989-758-709-2
AU - Harb S.
AU - Ahmad M.
AU - Swamy M.
PY - 2024
SP - 397
EP - 406
DO - 10.5220/0012716700003767
PB - SciTePress