Optimized Sample and Hold Design Leveraging MOSFETs Using SPICE Simulation

Soumya Sen, Atanu Chowdhury, Subarna Mondal, Agnibha Dasgupta

2024

Abstract

In order to reduce research, it emphasizes building a diminished-distortion sample and hold circuit, highlighting the importance of the MOSFET’s gate-to-source voltage being independent of the input. The circuit that is being demonstrated here runs quickly and doesn’t require an operational amplifier, which lowers power consumerism. Additionally, it harnesses the convenience of closely aligning transistor device S1 to the switching device, restricting distortion and mitigating drain-induced barrier lowering (DIBL) concerns. In linear platforms, sample and hold circuits are essential, particularly in some analog-to-digital converters. These converters generate a voltage inside and measure it versus the input voltage through a digital-to-analog converter (DAC). The input voltage uniformity is very important for precise adjustments during this test. The conversion phase ends when the voltages are accurately replicating the initial input and fall below a certain error limit.

Paper Citation

in Harvard Style

Sen S., Chowdhury A., Mondal S. and Dasgupta A. (2024). Optimized Sample and Hold Design Leveraging MOSFETs Using SPICE Simulation. In Proceedings of the 1st International Conference on Cognitive & Cloud Computing - Volume 1: IC3Com; ISBN 978-989-758-739-9, SciTePress, pages 85-89. DOI: 10.5220/0013278200004646

in Bibtex Style

@conference{ic3com24,
author={Soumya Sen and Atanu Chowdhury and Subarna Mondal and Agnibha Dasgupta},
title={Optimized Sample and Hold Design Leveraging MOSFETs Using SPICE Simulation},
booktitle={Proceedings of the 1st International Conference on Cognitive & Cloud Computing - Volume 1: IC3Com},
year={2024},
pages={85-89},
publisher={SciTePress},
organization={INSTICC},
doi={10.5220/0013278200004646},
isbn={978-989-758-739-9},
}

in EndNote Style

TY - CONF

JO - Proceedings of the 1st International Conference on Cognitive & Cloud Computing - Volume 1: IC3Com
TI - Optimized Sample and Hold Design Leveraging MOSFETs Using SPICE Simulation
SN - 978-989-758-739-9
AU - Sen S.
AU - Chowdhury A.
AU - Mondal S.
AU - Dasgupta A.
PY - 2024
SP - 85
EP - 89
DO - 10.5220/0013278200004646
PB - SciTePress