Logic Locking for Random Forests: Securing HDL Design and FPGA Accelerator Implementation

Rupesh Raj Karn, Johann Knechtel, Ozgur Sinanoglu

2025

Abstract

Logic locking has garnered significant attention due to its promising role in safeguarding intellectual property against potent threats across the integrated circuit supply chain. The locking mechanism introduces additional logic elements, so-called key-gates into a circuit, effectively securing the original design with a confidential key. This work utilizes locking to secure the hardware design of random-forest (RF) machine learning models. With the correct key, the design produces accurate inference outcomes; otherwise, it generates incorrect inferences. We explore field-programmable gate array (FPGA) implementation options to realize such locked inference accelerators. We propose an end-to-end methodology, spanning from the high-level RF hardware design, locking of those designs, to the FPGA implementation and performance evaluation. Our study employs Intel’s DE-10 standard FPGA, and we utilize multiple real-world datasets to illustrate the effectiveness of our approach.

Paper Citation

in Harvard Style

Karn R., Knechtel J. and Sinanoglu O. (2025). Logic Locking for Random Forests: Securing HDL Design and FPGA Accelerator Implementation. In Proceedings of the 11th International Conference on Information Systems Security and Privacy - Volume 2: ICISSP; ISBN 978-989-758-735-1, SciTePress, pages 463-473. DOI: 10.5220/0013108000003899

in Bibtex Style

@conference{icissp25,
author={Rupesh Karn and Johann Knechtel and Ozgur Sinanoglu},
title={Logic Locking for Random Forests: Securing HDL Design and FPGA Accelerator Implementation},
booktitle={Proceedings of the 11th International Conference on Information Systems Security and Privacy - Volume 2: ICISSP},
year={2025},
pages={463-473},
publisher={SciTePress},
organization={INSTICC},
doi={10.5220/0013108000003899},
isbn={978-989-758-735-1},
}

in EndNote Style

TY - CONF

JO - Proceedings of the 11th International Conference on Information Systems Security and Privacy - Volume 2: ICISSP
TI - Logic Locking for Random Forests: Securing HDL Design and FPGA Accelerator Implementation
SN - 978-989-758-735-1
AU - Karn R.
AU - Knechtel J.
AU - Sinanoglu O.
PY - 2025
SP - 463
EP - 473
DO - 10.5220/0013108000003899
PB - SciTePress